Built GDT + IDT + exception handlers
This commit is contained in:
+33
-1
@@ -2,7 +2,39 @@
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//! it as `@import("arch")` and never names x86_64 directly, so a second
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//! architecture is added by pointing that module at a different directory in
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//! build.zig — no change to the generic code. Keep everything CPU-specific here
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//! (halt now; GDT, IDT and paging will join it), and nothing generic.
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//! (halt, the descriptor tables, later paging), and nothing generic.
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const gdt = @import("gdt.zig");
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const idt = @import("idt.zig");
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/// The saved register/trap frame passed to a fault handler.
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pub const CpuState = idt.CpuState;
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/// Set up the CPU's descriptor tables: our own GDT, then the IDT with exception
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/// handlers. After this a CPU fault is reported instead of triple-faulting.
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/// Install the fault handler (setFaultHandler) first so early faults are caught.
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pub fn init() void {
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gdt.init();
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idt.init();
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}
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/// Route CPU exceptions to `handler`, which receives the trap frame and does not
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/// return. Until set, faults just halt the core.
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pub fn setFaultHandler(handler: *const fn (*const CpuState) noreturn) void {
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idt.on_fault = handler;
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}
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/// A human-readable name for a CPU exception vector.
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pub fn vectorName(vector: u64) []const u8 {
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return idt.vectorName(vector);
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}
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/// CR2 holds the faulting linear address after a page fault (#PF, vector 14).
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pub fn readCr2() u64 {
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return asm volatile ("mov %%cr2, %[out]"
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: [out] "=r" (-> u64),
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);
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}
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/// Park the core forever. `hlt` drops it into a low-power idle until the next
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/// interrupt; the loop re-halts on every wake so the stop is permanent. See
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@@ -0,0 +1,38 @@
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//! Global Descriptor Table. In long mode segmentation is mostly vestigial, but
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//! the CPU still needs valid code/data segment descriptors, and the IDT's gates
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//! reference a code selector — so we install our own flat GDT with known
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//! selectors (0x08 kernel code, 0x10 kernel data) rather than trusting whatever
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//! the firmware left in place.
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/// Selectors into the table below (index * 8).
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pub const kernel_code = 0x08;
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pub const kernel_data = 0x10;
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/// Flat 64-bit descriptors. Base/limit are ignored in long mode; what matters is
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/// the access byte and, for code, the long-mode (L) flag.
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/// code: present, ring 0, executable, readable, L=1 -> 0x00AF9A00_0000FFFF
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/// data: present, ring 0, writable -> 0x00CF9200_0000FFFF
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var table = [_]u64{
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0, // null descriptor (required)
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0x00AF9A000000FFFF, // kernel code
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0x00CF92000000FFFF, // kernel data
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};
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/// The operand `lgdt` wants: table byte-length minus one, then its address.
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const Descriptor = packed struct {
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limit: u16,
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base: u64,
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};
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/// Loads the GDT and reloads the segment registers (including CS). Defined in
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/// isr.s — it uses the selectors 0x08 (code) and 0x10 (data) that match `table`.
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extern fn gdt_flush(descriptor: *const Descriptor) callconv(.c) void;
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/// Install our GDT and switch onto its segments.
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pub fn init() void {
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const descriptor = Descriptor{
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.limit = @sizeOf(@TypeOf(table)) - 1,
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.base = @intFromPtr(&table),
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};
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gdt_flush(&descriptor);
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}
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@@ -0,0 +1,122 @@
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//! Interrupt Descriptor Table and the CPU-exception handlers. Without this, any
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//! fault (a stray pointer, a bad page-table entry) triple-faults and silently
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//! resets the machine. With it, the CPU vectors into our stubs, which capture the
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//! register state and hand it to a reporter that prints what went wrong.
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//!
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//! Only the 32 architecture-defined exception vectors are wired up here; device
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//! interrupts (the APIC, timer, keyboard) come later.
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const gdt = @import("gdt.zig");
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/// The register + trap frame the ISR stubs build on the stack, laid out so the
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/// lowest address (where RSP points when we call the handler) is the first field.
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/// See the push order in `isrCommon` below.
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pub const CpuState = extern struct {
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r15: u64,
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r14: u64,
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r13: u64,
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r12: u64,
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r11: u64,
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r10: u64,
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r9: u64,
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r8: u64,
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rbp: u64,
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rdi: u64,
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rsi: u64,
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rdx: u64,
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rcx: u64,
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rbx: u64,
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rax: u64,
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vector: u64, // pushed by the per-vector stub
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error_code: u64, // real one from the CPU, or 0 pushed by the stub
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rip: u64, // from here down: pushed by the CPU on entry
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cs: u64,
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rflags: u64,
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rsp: u64,
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ss: u64,
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};
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/// Where a fault is reported. The kernel overrides this (see setFaultHandler) with
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/// something that prints to the console; until then, just stop.
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pub var on_fault: *const fn (*const CpuState) noreturn = defaultFault;
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fn defaultFault(_: *const CpuState) noreturn {
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while (true) asm volatile ("hlt");
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}
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/// Names for the 32 defined exception vectors, for readable output.
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const names = [_][]const u8{
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"divide error", "debug",
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"NMI", "breakpoint",
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"overflow", "bound range exceeded",
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"invalid opcode", "device not available",
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"double fault", "coprocessor segment overrun",
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"invalid TSS", "segment not present",
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"stack-segment fault", "general protection fault",
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"page fault", "reserved (15)",
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"x87 floating-point", "alignment check",
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"machine check", "SIMD floating-point",
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"virtualization", "control protection",
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"reserved (22)", "reserved (23)",
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"reserved (24)", "reserved (25)",
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"reserved (26)", "reserved (27)",
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"hypervisor injection", "VMM communication",
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"security exception", "reserved (31)",
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};
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pub fn vectorName(vector: u64) []const u8 {
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return if (vector < names.len) names[vector] else "unknown";
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}
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/// A 64-bit IDT gate descriptor (16 bytes).
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const Gate = packed struct {
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offset_low: u16,
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selector: u16,
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ist: u8, // interrupt-stack-table index; 0 = use the current stack
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flags: u8, // present, DPL, gate type
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offset_mid: u16,
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offset_high: u32,
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reserved: u32 = 0,
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};
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var idt = [_]Gate{std.mem.zeroes(Gate)} ** 256;
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const Descriptor = packed struct {
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limit: u16,
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base: u64,
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};
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/// Loads the IDT (`lidt`). Defined in isr.s.
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extern fn idt_flush(descriptor: *const Descriptor) callconv(.c) void;
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fn setGate(vector: usize, handler: u64) void {
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idt[vector] = .{
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.offset_low = @truncate(handler),
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.selector = gdt.kernel_code,
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.ist = 0,
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.flags = 0x8E, // present, ring 0, 64-bit interrupt gate
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.offset_mid = @truncate(handler >> 16),
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.offset_high = @truncate(handler >> 32),
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};
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}
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/// Point the first 32 vectors at the stubs defined in isr.s and load the IDT.
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pub fn init() void {
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inline for (0..32) |vector| {
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const stub = @extern(*const anyopaque, .{ .name = std.fmt.comptimePrint("isr{d}", .{vector}) });
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setGate(vector, @intFromPtr(stub));
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}
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const descriptor = Descriptor{
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.limit = @sizeOf(@TypeOf(idt)) - 1,
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.base = @intFromPtr(&idt),
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};
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idt_flush(&descriptor);
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}
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/// Called by isr_common (isr.s) with a pointer to the trap frame. Exported so the
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/// assembly stubs can `call` it by name.
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export fn exceptionHandler(state: *const CpuState) callconv(.c) void {
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on_fault(state);
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}
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const std = @import("std");
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@@ -0,0 +1,123 @@
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# x86_64 low-level entry code: the CPU-exception stubs, plus the GDT/IDT load
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# helpers. Kept in a dedicated assembly file rather than inline asm because these
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# need real labels and cross-symbol jumps/calls (isr_common, exceptionHandler),
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# and because `lgdt`/`lidt` memory operands aren't expressible in Zig inline asm.
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#
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# Each exception vector normalises the stack to a uniform trap frame — a dummy
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# error code where the CPU pushes none, then the vector number — and jumps to the
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# shared tail, which saves the general registers and calls the Zig handler with a
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# pointer to the frame (matching src/arch/x86_64/idt.zig's CpuState).
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.text
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# gdt_flush(rdi = *GDT descriptor): load the GDT, reload the data segment
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# registers to the data selector, and reload CS to the code selector. CS can't be
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# set with mov, so we far-return through the caller's own return address.
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.global gdt_flush
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gdt_flush:
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lgdt (%rdi)
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mov $0x10, %ax # kernel data selector
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mov %ax, %ds
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mov %ax, %es
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mov %ax, %ss
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mov %ax, %fs
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mov %ax, %gs
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pop %rax # caller's return address
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push $0x08 # kernel code selector (new CS)
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push %rax # return address (new RIP)
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lretq
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# idt_flush(rdi = *IDT descriptor): load the IDT.
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.global idt_flush
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idt_flush:
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lidt (%rdi)
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ret
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# Stub for a vector the CPU does NOT push an error code for: push a dummy 0.
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.macro STUB_NOERR vec
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.global isr\vec
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isr\vec:
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pushq $0
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pushq $\vec
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jmp isr_common
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.endm
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# Stub for a vector the CPU DOES push an error code for: leave it in place.
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.macro STUB_ERR vec
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.global isr\vec
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isr\vec:
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pushq $\vec
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jmp isr_common
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.endm
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STUB_NOERR 0
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STUB_NOERR 1
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STUB_NOERR 2
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STUB_NOERR 3
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STUB_NOERR 4
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STUB_NOERR 5
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STUB_NOERR 6
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STUB_NOERR 7
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STUB_ERR 8
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STUB_NOERR 9
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STUB_ERR 10
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STUB_ERR 11
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STUB_ERR 12
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STUB_ERR 13
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STUB_ERR 14
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STUB_NOERR 15
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STUB_NOERR 16
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STUB_ERR 17
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STUB_NOERR 18
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STUB_NOERR 19
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STUB_NOERR 20
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STUB_ERR 21
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STUB_NOERR 22
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STUB_NOERR 23
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STUB_NOERR 24
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STUB_NOERR 25
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STUB_NOERR 26
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STUB_NOERR 27
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STUB_NOERR 28
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STUB_NOERR 29
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STUB_NOERR 30
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STUB_NOERR 31
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.extern exceptionHandler
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# Shared tail. Register push order here defines the CpuState field order.
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isr_common:
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push %rax
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push %rbx
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push %rcx
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push %rdx
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push %rsi
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push %rdi
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push %rbp
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push %r8
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push %r9
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push %r10
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push %r11
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push %r12
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push %r13
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push %r14
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push %r15
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mov %rsp, %rdi # first argument: pointer to the trap frame
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call exceptionHandler
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pop %r15
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pop %r14
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pop %r13
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pop %r12
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pop %r11
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pop %r10
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pop %r9
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pop %r8
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pop %rbp
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pop %rdi
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pop %rsi
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pop %rdx
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pop %rcx
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pop %rbx
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pop %rax
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add $16, %rsp # drop the vector and error code
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iretq
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+20
-15
@@ -30,6 +30,11 @@ fn kmain(boot_info: *const BootInfo) noreturn {
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con.clear();
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con_ready = true;
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// Catch CPU exceptions before doing anything that might fault: install our
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// reporter, then bring up the GDT + IDT.
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arch.setFaultHandler(onException);
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arch.init();
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con.write("danos: framebuffer console online\n");
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con.print(" resolution : {d}x{d}\n", .{ fb.width, fb.height });
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con.print(" pitch : {d} bytes\n", .{fb.pitch});
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@@ -76,21 +81,6 @@ fn kmain(boot_info: *const BootInfo) noreturn {
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if (f2) |p| pmm.free(p);
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con.print(" after free : {d} frames free\n", .{pmm.stats().free_frames});
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// Bring up the physical frame allocator over that map, and prove it works:
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// allocate three frames, then hand them back.
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pmm.init(boot_info.memory_map);
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const s = pmm.stats();
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con.print("\ndanos: frame allocator online\n", .{});
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con.print(" free frames: {d} ({d} MiB)\n", .{ s.free_frames, s.free_frames * danos.page_size / (1024 * 1024) });
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const f0 = pmm.alloc();
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const f1 = pmm.alloc();
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const f2 = pmm.alloc();
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con.print(" alloc x3 : 0x{x} 0x{x} 0x{x}\n", .{ f0 orelse 0, f1 orelse 0, f2 orelse 0 });
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if (f0) |p| pmm.free(p);
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if (f1) |p| pmm.free(p);
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if (f2) |p| pmm.free(p);
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con.print(" after free : {d} frames free\n", .{pmm.stats().free_frames});
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con.write("\nkernel initialised; nothing left to do, halting.\n");
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arch.halt();
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@@ -101,6 +91,21 @@ fn mib(pages: u64) u64 {
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return pages * danos.page_size / (1024 * 1024);
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}
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/// Report a CPU exception in red and halt. There's no fault recovery yet, so any
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/// exception is terminal — but now it prints what and where instead of silently
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/// resetting the machine.
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fn onException(state: *const arch.CpuState) noreturn {
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if (con_ready) {
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con.fg = 0x00ff_5555;
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con.print("\nCPU EXCEPTION: {s} (vector {d})\n", .{ arch.vectorName(state.vector), state.vector });
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con.print(" error code : 0x{x}\n", .{state.error_code});
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con.print(" RIP : 0x{x:0>16}\n", .{state.rip});
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con.print(" RSP : 0x{x:0>16}\n", .{state.rsp});
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if (state.vector == 14) con.print(" CR2 (addr) : 0x{x:0>16}\n", .{arch.readCr2()});
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}
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arch.halt();
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}
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/// Freestanding has no OS to receive a panic. Print it to the console (if it is
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/// up yet) in red, then halt.
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pub const panic = std.debug.FullPanic(struct {
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