The PCI scan from ring 3: pci-bus walks the ECAM it mapped (M19.1)
The manager matches the pci_host_bridge node and spawns pci-bus with the bridge id as its assignment — hello, supervision, restart, all the M18 contract for free. The driver claims the bridge, maps the ECAM window (resource 0) through the ordinary mmio grant, and repeats the kernel's brute-force bus/device/function walk from user space. The pci-scan scenario builds its expected marker from the kernel's own function count, so the two enumerations must agree exactly — the equivalence that licenses retiring the kernel walk in M19.3.
This commit is contained in:
Daniel Samson
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//! /system/drivers/pci-bus — the PCI bus driver: enumeration moved out of ring 0
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//! (docs/m19-m20-plan.md, M19). The device manager matches the `pci_host_bridge`
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//! node and spawns one instance per bridge, the bridge's device id as argv[1] —
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//! the same per-device contract as usb-xhci-bus.
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//!
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//! M19.1 (this increment): claim the bridge, map its ECAM window (resource 0;
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//! the bus range and the MMIO apertures follow it), walk every
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//! bus/device/function config header, and log what the walk finds — ending
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//! with "pci-bus: N functions found", which the `pci-scan` scenario compares
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//! against the kernel's own enumeration. Registration and reports (M19.2), and
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//! the kernel walk's retirement (M19.3), build on this proven-equivalent scan.
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const std = @import("std");
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const runtime = @import("runtime");
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const protocol = runtime.device_manager_protocol;
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const device = runtime.device;
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fn writeLine(comptime fmt: []const u8, arguments: anytype) void {
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var line: [128]u8 = undefined;
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_ = runtime.system.write(std.fmt.bufPrint(&line, fmt, arguments) catch return);
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}
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var bridge_id: u64 = protocol.no_device;
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var ecam_base: usize = 0;
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var start_bus: u64 = 0;
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var bus_count: u64 = 0;
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/// One aligned 32-bit read from a function's configuration space.
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fn configRead(bus: u64, dev: u64, function: u64, offset: u64) u32 {
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const address = ecam_base + (((bus - start_bus) << 20) | (dev << 15) | (function << 12) | offset);
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const register: *volatile u32 = @ptrFromInt(address);
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return register.*;
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}
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/// Claim the bridge, map the ECAM, hello the manager, then scan.
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fn initialise(endpoint: runtime.ipc.Handle) bool {
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_ = endpoint;
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if (!device.claim(bridge_id)) {
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writeLine("pci-bus: unable to claim bridge device {d}\n", .{bridge_id});
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return false;
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}
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const buffer = runtime.allocator().alloc(device.DeviceDescriptor, 64) catch {
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_ = runtime.system.write("pci-bus: out of memory\n");
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return false;
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};
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const total = device.enumerate(buffer);
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const descriptor = for (buffer[0..@min(total, buffer.len)]) |d| {
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if (d.id == bridge_id) break d;
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} else {
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writeLine("pci-bus: device {d} not in the device tree\n", .{bridge_id});
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return false;
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};
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// Resource 0 is the ECAM window (1 MiB of config space per bus); the bus
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// range rides beside it. The MMIO apertures (M19.0) come after both.
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if (descriptor.resource_count < 2 or descriptor.resources[0].kind != @intFromEnum(device.ResourceKind.memory)) {
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_ = runtime.system.write("pci-bus: bridge has no ECAM window\n");
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return false;
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}
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const bus_range = for (descriptor.resources[0..@intCast(descriptor.resource_count)]) |resource| {
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if (resource.kind == @intFromEnum(device.ResourceKind.bus_range)) break resource;
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} else {
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_ = runtime.system.write("pci-bus: bridge has no bus range\n");
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return false;
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};
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start_bus = bus_range.start;
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bus_count = bus_range.len;
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ecam_base = device.mmioMap(bridge_id, 0) orelse {
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_ = runtime.system.write("pci-bus: ECAM mmio_map failed\n");
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return false;
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};
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// The handshake, then the scan (reports join in M19.2).
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var manager: ?runtime.ipc.Handle = null;
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var tries: u32 = 0;
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while (manager == null and tries < 100) : (tries += 1) {
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manager = runtime.ipc.lookup(.device_manager);
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if (manager == null) runtime.system.sleep(20);
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}
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const h = manager orelse {
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_ = runtime.system.write("pci-bus: no device manager to hello\n");
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return false;
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};
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const hello = protocol.Hello{ .role = @intFromEnum(protocol.Role.bus), .device_id = bridge_id };
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var reply: [protocol.message_maximum]u8 = undefined;
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const n = runtime.ipc.call(h, std.mem.asBytes(&hello), &reply) catch {
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_ = runtime.system.write("pci-bus: hello call failed\n");
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return false;
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};
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if (n < protocol.reply_size or std.mem.bytesToValue(protocol.HelloReply, reply[0..protocol.reply_size]).status != 0) {
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_ = runtime.system.write("pci-bus: hello refused\n");
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return false;
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}
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scan();
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return true;
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}
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/// The brute-force walk the kernel does today, from ring 3: every bus in the
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/// range, 32 devices, 8 functions; vendor id FFFFh means nothing decodes there,
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/// and only multifunction devices get their functions 1..7 probed.
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fn scan() void {
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var found: u32 = 0;
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var bus: u64 = start_bus;
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while (bus < start_bus + bus_count) : (bus += 1) {
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var dev: u64 = 0;
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while (dev < 32) : (dev += 1) {
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const first = configRead(bus, dev, 0, 0);
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if (first & 0xFFFF == 0xFFFF) continue;
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const multifunction = (configRead(bus, dev, 0, 0x0C) >> 16) & 0x80 != 0;
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var function: u64 = 0;
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while (function < 8) : (function += 1) {
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if (function != 0 and !multifunction) break;
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const vendor_device = configRead(bus, dev, function, 0);
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if (vendor_device & 0xFFFF == 0xFFFF) continue;
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const class_revision = configRead(bus, dev, function, 0x08);
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found += 1;
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writeLine("pci-bus: {d}:{d}.{d} class 0x{x:0>6}\n", .{ bus, dev, function, class_revision >> 8 });
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}
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}
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}
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writeLine("pci-bus: {d} functions found\n", .{found});
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}
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fn onMessage(message: []const u8, reply: []u8, sender: u32, capability: ?runtime.ipc.Handle) usize {
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_ = message;
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_ = reply;
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_ = sender;
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_ = capability;
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return 0;
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}
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pub fn main(init: runtime.process.Init) void {
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const argument = init.arguments.get(1) orelse return; // bare (ramdisk sweep): stay silent
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bridge_id = std.fmt.parseInt(u64, argument, 10) catch {
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writeLine("pci-bus: malformed bridge device id '{s}'\n", .{argument});
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return;
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};
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runtime.service.run(protocol.message_maximum, .{
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.init = initialise,
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.on_message = onMessage,
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});
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}
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pub const panic = runtime.panic;
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comptime {
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_ = &runtime.start._start; // pull the runtime entry shim into the image
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}
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