M11–M12: IRQ-as-IPC and bus drivers; expand names tree-wide
Two driver-model milestones plus a tree-wide naming pass. Suite 35/35 (QEMU) + host tests green. M11 — IRQ-as-IPC. A ring-3 driver now sleeps until its device interrupts it. New src/kernel/irq.zig: per-GSI endpoint bindings, comptime per-vector trampolines, dispatch = mask GSI -> LAPIC EOI -> notifyLocked, all under one lock region. irq_bind/irq_ack syscalls, gated by the device claim like mmio_map. interruptDispatch no longer EOIs — each handler owns its EOI, because a level line must be masked before it is acknowledged (irq_ack is the unmask). Bindings are keyed on the owning task and released on exit (a shared endpoint's siblings survive). hpetd rewritten interrupt-driven. Tests: hpet (rewritten, reads back the I/O APIC routing) and irqfree. M12 — bus drivers. DeviceDesc gains a parent, making the device table a tree. dev_register (device_register) lets a process publish children below a device it claimed; the kernel enforces resource containment (a child's resources must nest in its parent's), so a descriptor can't fabricate a window over kernel RAM. Descriptor copied in via copyFromUser (physmap walk — an unmapped user pointer fails the call instead of faulting the kernel). Per-parent child cap bounds table exhaustion. sbin/busd.zig is a worked bus driver. Test: bus. Naming — per docs/coding-standards.md: non-acronym abbreviations spelled out (message, descriptor, device_service, scheduler, runtime, physical, interpreter, ...); acronyms kept (IPC, MMIO, DMA, HCD, ...); files are kebab-case (ipc-synchronous.zig, device-service.zig, vfs-protocol.zig, ...). Exceptions: POSIX/C ABI names and Zig idioms (init/len/ptr) kept. Module collisions resolved by specific naming (config -> parameters, device.zig alias -> device_model). AML op/Op disambiguated: op = opcode, Op = operation; per-opcode parse handlers renamed opX -> parseX. New driver docs: drivers.md, driver-model.md (bus/class/HCD shapes + the proposed M13–M16 ABI), coding-standards.md.
This commit is contained in:
Daniel Samson
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@@ -1,75 +1,187 @@
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//! /sbin/hpetd — a user-space HPET driver, the first real device driver. It
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//! proves IO passthrough end to end: enumerate the device table, find the HPET
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//! (a timer with an MMIO window), claim it, map its registers directly into this
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//! ring-3 address space (strong-uncacheable), then drive the hardware — enable
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//! the main counter and read it. If the counter advances, a user process is
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//! touching real hardware through a kernel-granted MMIO mapping.
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//! /sbin/hpetd — a user-space HPET driver. It proves the whole driver model end to
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//! end: enumerate the device table, find the HPET, claim it, map its registers into
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//! this ring-3 address space (strong-uncacheable), **bind its interrupt to an IPC
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//! endpoint**, then sit blocked in `replyWait` until the hardware wakes it.
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//!
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//! Register offsets (HPET spec): general config = 0x10 (bit 0 = ENABLE),
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//! main counter = 0xF0.
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//! Nothing here polls. Between interrupts the process is `.blocked` and off every
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//! scheduler queue; the core runs other work or idles. That is the point of the
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//! exercise — a driver is a process that sleeps until its device has something to
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//! say (see docs/drivers.md).
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//!
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//! The comparator is configured **level-triggered** on purpose. Edge would be
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//! simpler, but level is the discipline every real device line needs, and it forces
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//! the full cycle to be correct:
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//!
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//! kernel ISR mask the GSI -> EOI -> notify this endpoint
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//! hpetd wake, clear GENERAL_INT_STATUS (deasserts the line), re-arm
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//! hpetd irq_ack -> kernel unmasks the GSI
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//!
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//! Clear the status bit *before* acking, or the line is still asserted when the
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//! kernel unmasks and the I/O APIC redelivers forever.
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//!
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//! Register map (HPET spec 1.0a):
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//! 0x000 GENERAL_CAP [63:32] fs per tick, [12:8] number timers - 1
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//! 0x010 GENERAL_CONFIGURATION bit0 ENABLE_CNF, bit1 LEG_RT_CNF
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//! 0x020 GENERAL_INT_STATUS bit n = timer n asserted (write 1 to clear)
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//! 0x0F0 MAIN_COUNTER
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//! 0x100 TIMER0_CONFIGURATION bit1 INT_TYPE(1=level) bit2 INT_ENB bit3 TYPE(periodic)
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//! bits[13:9] INT_ROUTE, [63:32] INT_ROUTE_CAP
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//! 0x108 TIMER0_COMPARATOR
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const rt = @import("rt");
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const dev = rt.dev;
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const runtime = @import("runtime");
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const device = runtime.device;
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const ipc = runtime.ipc;
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const register_general_cap = 0x000;
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const register_general_configuration = 0x010;
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const register_int_status = 0x020;
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const register_main_counter = 0x0F0;
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const register_timer0_configuration = 0x100;
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const register_timer0_comparator = 0x108;
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const configuration_enable: u64 = 1 << 0; // GENERAL_CONFIGURATION.ENABLE_CNF
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const configuration_leg_rt: u64 = 1 << 1; // GENERAL_CONFIGURATION.LEG_RT_CNF
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const tn_int_type_level: u64 = 1 << 1;
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const tn_int_enb: u64 = 1 << 2;
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const tn_type_periodic: u64 = 1 << 3;
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const tn_route_shift = 9;
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const tn_route_mask: u64 = 0x1F << tn_route_shift;
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/// Interrupts to observe before declaring victory.
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const target_ticks = 5;
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fn register(base: usize, off: usize) *volatile u64 {
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return @ptrFromInt(base + off);
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}
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/// A timer-class device exposing both an MMIO window and an IRQ: its id, the two
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/// resource indices, and the GSI discovery chose out of `Tn_INT_ROUTE_CAP`.
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const Found = struct { device_id: u64, mmio: u64, irq: u64, gsi: u64 };
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fn findHpet(buffer: []device.DeviceDescriptor) ?Found {
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const total = device.enumerate(buffer);
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const n = @min(total, buffer.len);
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for (buffer[0..n]) |d| {
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if (d.class != @intFromEnum(device.DeviceClass.timer)) continue;
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// Skip comparator children a bus driver may have published below the block
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// (see sbin/busd.zig) — we want the register block itself.
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if (d.parent != device.no_parent) continue;
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var mmio: ?u64 = null;
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var irq: ?u64 = null;
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for (0..d.resource_count) |j| {
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switch (d.resources[j].kind) {
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@intFromEnum(device.ResourceKind.memory) => mmio = mmio orelse j,
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@intFromEnum(device.ResourceKind.irq) => irq = irq orelse j,
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else => {},
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}
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}
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if (mmio) |m| if (irq) |i| {
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return .{ .device_id = d.id, .mmio = m, .irq = i, .gsi = d.resources[i].start };
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};
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}
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return null;
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}
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pub fn main() void {
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// Enumerate into a heap buffer (too big for the one-page user stack).
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const buf = rt.allocator().alloc(dev.DeviceDesc, 32) catch {
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_ = rt.sys.write("hpetd: out of memory\n");
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return;
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};
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const total = dev.enumerate(buf);
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const n = @min(total, buf.len);
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// Find a timer-class device with an MMIO resource (the HPET).
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var dev_id: u64 = 0;
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var res_idx: u64 = 0;
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var found = false;
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var i: usize = 0;
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outer: while (i < n) : (i += 1) {
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const d = buf[i];
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if (d.class != @intFromEnum(dev.DeviceClass.timer)) continue;
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var j: usize = 0;
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while (j < d.resource_count) : (j += 1) {
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if (d.resources[j].kind == @intFromEnum(dev.ResourceKind.memory)) {
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dev_id = d.id;
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res_idx = j;
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found = true;
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break :outer;
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}
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}
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}
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if (!found) {
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_ = rt.sys.write("hpetd: no HPET found\n");
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return;
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}
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if (!dev.claim(dev_id)) {
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_ = rt.sys.write("hpetd: claim failed\n");
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return;
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}
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const base = dev.mmioMap(dev_id, res_idx) orelse {
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_ = rt.sys.write("hpetd: mmio_map failed\n");
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const buffer = runtime.allocator().alloc(device.DeviceDescriptor, 32) catch {
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_ = runtime.system.write("hpetd: out of memory\n");
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return;
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};
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// Drive the hardware: enable the counter (an MMIO write), then read it twice.
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const config: *volatile u64 = @ptrFromInt(base + 0x10);
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config.* |= 1; // ENABLE
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const counter: *volatile u64 = @ptrFromInt(base + 0xF0);
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const a = counter.*;
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rt.sys.sleep(50);
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const b = counter.*;
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const hpet = findHpet(buffer) orelse {
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_ = runtime.system.write("hpetd: no HPET with an IRQ\n");
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return;
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};
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if (b > a) {
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while (true) {
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_ = rt.sys.write("hpetd: ok\n");
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rt.sys.sleep(1000);
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if (!device.claim(hpet.device_id)) {
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_ = runtime.system.write("hpetd: claim failed\n");
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return;
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}
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const base = device.mmioMap(hpet.device_id, hpet.mmio) orelse {
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_ = runtime.system.write("hpetd: mmio_map failed\n");
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return;
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};
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// The GSI discovery picked for us out of Tn_INT_ROUTE_CAP. Program the comparator
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// to raise exactly this line — the kernel will only bind the one it recorded.
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const gsi = hpet.gsi;
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const endpoint = ipc.createEndpoint() orelse {
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_ = runtime.system.write("hpetd: create_endpoint failed\n");
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return;
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};
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// --- program the hardware ------------------------------------------------
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// Counter period, so we can arm the comparator a fixed wall-clock distance out.
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const femtos_per_tick = register(base, register_general_cap).* >> 32;
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if (femtos_per_tick == 0) {
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_ = runtime.system.write("hpetd: bad HPET period\n");
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return;
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}
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const ticks_per_ms = 1_000_000_000_000 / femtos_per_tick;
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// Stop the counter and take the legacy route off while we reconfigure.
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register(base, register_general_configuration).* &= ~(configuration_enable | configuration_leg_rt);
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// Timer 0: one-shot, level-triggered, routed to our GSI, interrupt enabled.
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// One-shot (not periodic) sidesteps the HPET's Tn_value_SET accumulator quirk —
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// we simply re-arm from the driver on each interrupt, which is what a tickless
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// timer driver does anyway.
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var t0 = register(base, register_timer0_configuration).*;
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t0 &= ~(tn_route_mask | tn_type_periodic);
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t0 |= tn_int_type_level | tn_int_enb | (gsi << tn_route_shift);
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register(base, register_timer0_configuration).* = t0;
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// Clear any stale assertion, then arm ~100 ms out and start the counter.
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register(base, register_int_status).* = 1;
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register(base, register_timer0_comparator).* = register(base, register_main_counter).* + ticks_per_ms * 100;
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register(base, register_general_configuration).* |= configuration_enable;
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if (!device.irqBind(hpet.device_id, hpet.irq, endpoint)) {
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_ = runtime.system.write("hpetd: irq_bind failed\n");
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return;
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}
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_ = runtime.system.write("hpetd: bound, sleeping until the hardware speaks\n");
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// --- the driver loop -----------------------------------------------------
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// Blocked in replyWait. No polling, no spinning: the next line of this function
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// runs only because an interrupt fired.
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var receive: [64]u8 = undefined;
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var count: usize = 0;
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while (count < target_ticks) {
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// Blocked here. The task is `.blocked` and off every scheduler queue; the
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// next line runs only because the HPET raised its line.
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const r = ipc.replyWait(endpoint, &.{}, &receive);
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if (!r.isNotification()) continue; // a client request, not our IRQ
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// Quiet the device: write 1 to timer 0's status bit. Until this lands, the
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// line is still asserted and unmasking would refire immediately.
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register(base, register_int_status).* = 1;
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count += 1;
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if (count < target_ticks) {
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register(base, register_timer0_comparator).* = register(base, register_main_counter).* + ticks_per_ms * 100;
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} else {
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// Last one: stop the source rather than re-arming, so the line is left
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// both quiet *and* unmasked by the ack below. Re-arming here would leave
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// a pending interrupt that nobody is waiting for, and the ISR would mask
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// the line again a moment later.
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register(base, register_timer0_configuration).* &= ~tn_int_enb;
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}
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_ = runtime.system.write("hpetd: irq\n");
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if (!device.irqAck(hpet.device_id, hpet.irq)) {
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_ = runtime.system.write("hpetd: irq_ack failed\n");
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return;
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}
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}
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_ = rt.sys.write("hpetd: counter stuck\n");
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_ = runtime.system.write("hpetd: ok\n");
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while (true) runtime.system.sleep(1000);
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}
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pub const panic = rt.panic;
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pub const panic = runtime.panic;
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comptime {
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_ = &rt.start._start;
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_ = &runtime.start._start;
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}
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