add device platform module with ACPI support

src/kernel/arch/x86_64/cpu.zig

@@ -11,6 +11,7 @@ const idt = @import("idt.zig");
 const paging = @import("paging.zig");
 const serial = @import("serial.zig");
 const apic = @import("apic.zig");
+const io = @import("io.zig");
 
 /// The saved register/trap frame passed to a fault handler.
 pub const CpuState = idt.CpuState;
@@ -177,6 +178,28 @@ pub fn vectorName(vector: u64) []const u8 {
     return idt.vectorName(vector);
 }
 
+/// Read `width` bytes (1/2/4) from an I/O port. The generic device layer drives
+/// ACPI registers through this rather than naming x86 port instructions; on an
+/// MMIO-only architecture this would be implemented differently.
+pub fn pioRead(width: u8, port: u16) u32 {
+    return switch (width) {
+        1 => io.inb(port),
+        2 => io.inw(port),
+        4 => io.inl(port),
+        else => 0,
+    };
+}
+
+/// Write `width` bytes (1/2/4) to an I/O port.
+pub fn pioWrite(width: u8, port: u16, value: u32) void {
+    switch (width) {
+        1 => io.outb(port, @truncate(value)),
+        2 => io.outw(port, @truncate(value)),
+        4 => io.outl(port, value),
+        else => {},
+    }
+}
+
 /// CR2 holds the faulting linear address after a page fault (#PF, vector 14).
 pub fn readCr2() u64 {
     return asm volatile ("mov %%cr2, %[out]"