Add runtime.time, drop demo drivers, harden TSC timekeeping

Time is a kernel concern in danos: the kernel owns the scheduling timer and
already exposes monotonic time via the clock/sleep/timer_bind syscalls, so a
userspace time service would be a redundant, slower path. This adds the generic
runtime.time module over those syscalls, retires the two demonstration drivers,
reorganizes the milestone docs, and makes the monotonic clock correct on Intel,
AMD, and inside any VM.

runtime.time (library/runtime/time.zig)
- Instant/Duration interface: now, sleep, spin, after, monotonicNanos, available
- a thin layer over system.clock/sleep/timerOnce; unit-tested arithmetic

Remove the demo drivers hpet and bus (a teaching example belongs in the docs,
not shipped in the tree)
- system/drivers/ now holds only real drivers: pci-bus, ps2-bus, usb-xhci-bus
- device-manager end-to-end test repointed to pci-bus (asserts on kernel state:
  the process table and the device tree, not a racy serial marker)
- device_register containment moved to a new in-kernel `containment` test
- the driver-model worked example moved inline into docs/drivers.md

Reorganize milestone docs into topic docs
- m17-m18 / m19-m20 / m21 plans dissolved into process-lifecycle, device-manager,
  discovery, and acpi docs; new docs/power.md and docs/timers.md; ~20 citations
  repointed; plan docs deleted

TSC reliability (apic.zig, smp.zig, cpu.zig, kernel.zig)
- check the invariant-TSC bit (CPUID 0x80000007 EDX[8]) on Intel and AMD
- cross-core "warp" check at SMP bring-up, pairwise BSP<->AP as each core comes up
- fall back to the HPET clocksource when the TSC is not invariant (a bare VM) or
  not synchronized (a warp), switched continuously so time never jumps
- boot log reports the outcome; new tsc-sync test exercises the TSC + warp path

Verified: zig build; zig build test; 60/60 QEMU cases (incl. new containment and
tsc-sync).

system/devices/acpi.zig

@@ -159,7 +159,7 @@ pub var dsdt_physical: u64 = 0;
 
 /// The FADT itself (physical + length), published on the acpi-tables node so
 /// the ring-3 acpi service can read the PM1 event and GPE blocks it needs for
-/// the event side (docs/m21-plan.md decision 3). Distinguished from the AML
+/// the event side (docs/acpi.md — ACPI events). Distinguished from the AML
 /// blob resources by its intact "FACP" header — the blobs are header-stripped.
 var fadt_physical: u64 = 0;
 var fadt_length: u64 = 0;
@@ -423,7 +423,7 @@ pub fn discover(rsdp_physical: u64, memory_regions: []const boot_handoff.MemoryR
         // whatever the FADT alone provided.
     }
 
-    // Publish the acpi-tables node (docs/m19-m20-plan.md M20): the AML blobs as
+    // Publish the acpi-tables node (docs/discovery.md): the AML blobs as
     // memory resources for the acpi service to map and parse in ring 3, a broad
     // io_port grant for the OperationRegion access its interpreter needs, and
     // the SCI for the events track (M21). Exactly one node, one trusted
@@ -448,7 +448,7 @@ fn publishAcpiTablesNode(device_tree: *DeviceTree) !void {
     // The broad I/O grant: OperationRegions name whatever ports the firmware
     // chose (EC, PM1, GPE, SMBus); which ports cannot be known before the AML
     // that names them is parsed, so the grant is the whole space — the honest
-    // trust boundary of docs/m19-m20-plan.md decision 5.
+    // trust boundary of docs/discovery.md (the acpi service's one trusted node).
     _ = node.addResource(.io_port, 0, 1 << 16);
     // A broad interrupt window: ACPI _CRS names legacy ISA IRQs (the PS/2 lines
     // 1 and 12, the RTC, …), and the service registers those devices under this
@@ -610,7 +610,7 @@ fn parseMcfg(device_tree: *DeviceTree, header: *const SystemDescriptorTableHeade
 var boot_memory_regions: []const boot_handoff.MemoryRegion = &.{};
 
 /// The bridge's MMIO apertures, derived from the boot memory map's holes
-/// (docs/m19-m20-plan.md decision 2): registered PCI functions carry BAR
+/// (docs/discovery.md — apertures from the memory map): registered PCI functions carry BAR
 /// resources, and `device_register` containment demands the bridge own windows
 /// that cover them. Everything the firmware described is "not hole"; the low
 /// aperture runs from the end of the described space below 4 GiB up to the