M15: interrupts for PCI devices (ECAM config space + MSI)

Two parts, both blockers for real PCI drivers.

ECAM config space per function: enumeratePci now gives every pci_device its own 4 KiB
configuration window as resource 0. A claimed PCI driver mmio_maps that to reach its
command register, BARs, and — the point — its capability list (MSI/MSI-X, PCIe extended
caps), with no new syscall. Verified in the discovery test (QEMU q35's functions each
carry it).

MSI: msi_bind(device_id, endpoint) -> address (rax), data (rdx) allocates a per-device
edge-triggered vector, binds it to the endpoint, and returns the (address, data) the
driver programs into its own MSI capability. Unlike irq_bind there's no GSI, no I/O APIC
entry, no sharing, and no ack cycle — dispatch recognises an MSI vector (vector_gsi ==
none, msi_bound set), EOIs, and notifies. Owner-keyed release drops the binding on exit.
Legacy INTx (_PRT parsing + shared lines) is deliberately skipped; MSI is the real
answer.

QEMU's HPET has no MSI, so the new `msi` test proves the vector-routing path with a
self-IPI (new apic.selfIpi) standing in for the device's MSI write: bind a vector,
fire it, the bound endpoint is notified. The msi_bind syscall wraps irq.msiBind with
the claim check and lands its first real use with the first PCI driver. Suite 39/39
plus host tests.

system/kernel/architecture/x86_64/cpu.zig

@@ -424,6 +424,12 @@ pub fn irqEoi() void {
     apic.eoi();
 }
 
+/// Send this core a fixed interrupt at `vector`. Stands in for a device's MSI write
+/// so the MSI vector-routing path can be exercised without MSI-capable hardware.
+pub fn selfIpi(vector: u8) void {
+    apic.selfIpi(vector);
+}
+
 /// Enable the Local APIC, calibrate its timer against the best available reference
 /// (see apic.calibrate — no longer the PIT by default), and start it firing at
 /// `timer_hz` — the kernel's real-time heartbeat. Interrupts still have to be