docs: audit all 'what's next' sections against the code; fix stale comments

Verified every deferred item in the nine docs with a what's-next section and
marked what has since landed (reaper, per-process CR3, higher-half kernel,
kernel heap, contiguous frame alloc, RSDP capture, cap-passing, driver restart
with backoff, PS/2 keyboard) while keeping the genuinely open items. Also
corrects interrupts.md's claim that the keyboard skipped the IO-APIC, and
updates scheduler.zig/heap.zig comments that predated the reaper and the big
kernel lock.
This commit is contained in:
Daniel Samson
2026-07-22 02:23:51 +01:00
parent a081f69def
commit 52df2ba6f6
11 changed files with 98 additions and 77 deletions
+11 -9
View File
@@ -188,13 +188,15 @@ spinning in unrelated code — is the whole mechanism working end to end.
- **Uncacheable MMIO**: device grants are mapped `PCD|PWT` (strong-uncacheable) for
user drivers — see [paging.md](paging.md).
## What's next (not done here)
## What's next (partly done since)
- **The keyboard**: the PS/2 controller is port-mapped (`0x60`/`0x64`), and port I/O is
now available to ring 3 via the claim-gated `io_read`/`io_write` syscalls
([drivers.md](drivers.md)) — so the first *input* device is unblocked; it just needs
writing (claim the controller, `irq_bind` GSI 1, read scancodes from `0x60`).
- **MSI-X**: `msi_bind` gives one per-device edge-triggered vector (M15); MSI-X's
multi-vector table (many queues per device, e.g. NVMe) is the remaining extension.
- **The LAPIC's own page** is still mapped writeback-cacheable like the rest of the
identity map. QEMU tolerates it; real hardware wants it uncacheable.
- **The keyboard** — done, exactly as sketched: the PS/2 bus driver
(`system/drivers/ps2-bus/`) claims the port-mapped 8042 controller through the
claim-gated `io_read`/`io_write` syscalls ([drivers.md](drivers.md)), binds
IRQ 1 (and the aux mouse's IRQ 12), reads scancodes from `0x60`, and decodes
them into HID events for the [input service](input.md).
- **MSI-X** — still open: `msi_bind` gives one per-device edge-triggered vector
(M15); MSI-X's multi-vector table (many queues per device, e.g. NVMe) is the
remaining extension.
- **The LAPIC's own page** — still mapped writeback-cacheable like the rest of
the identity map. QEMU tolerates it; real hardware wants it uncacheable.