kernel: ring 0 reaches user memory only through the checked copy

SMAP makes the rule the copy layer has followed since it was written into a
rule the hardware keeps. A ring-0 read or write of a user page now faults,
so any code that reaches for a user pointer directly fails the first time it
runs rather than the first time someone attacks it — and the suite becomes
the enforcement test, because every case exercises the kernel with the bit
on. Nothing had to be fixed to turn it on, which is the retrospective proof
that the nine stragglers converted earlier were all of them.

The interrupt entry needed one instruction first. Hardware does not clear
the alignment-check flag on its way into a handler, and ring 3 sets that
flag freely, so a process could have taken an interrupt with SMAP suspended
for the duration. The system call path was already covered — its flag mask
clears it — but the interrupt path needed a `clac`, which cannot simply be
assembled in: it is an invalid instruction on a processor without SMAP, and
danos boots on those too. So the entry ships as a three-byte NOP and is
patched at boot, through the physmap, because the kernel maps its own text
read-only.

The ordering that makes that safe is enforced rather than described: the
patch sets a flag, and no core will set the SMAP bit until it is true. A
translation that fails, or bytes that read back wrong through the address
they will actually be fetched from, leave the machine unhardened and saying
so — which is the same posture the IOMMU takes, and better than enforcing
over an entry path that cannot comply. The patch runs before interrupts are
enabled and before any second core exists; a comment says so, because the
three bytes pass through an encoding that must never be executed and a
future change that moves this later has to deal with that first.

Suite 114/114, with a case that reads a user page from ring 0 and requires
the fault, and the multi-core case asserting every core that ran work had
the bit — the same shape SMEP got, for the same reason: CR4 is per-core, and
a hardening is only as wide as its narrowest core.

system/kernel/architecture/x86_64/cpu.zig

@@ -150,9 +150,16 @@ pub fn init() void {
     tss.init();
     idt.init();
     pcpu.initSystemCall();
+    // The machine-wide half of SMAP, and it must precede every CR4 write: the
+    // interrupt entry has to be able to clear EFLAGS.AC before any core claims the
+    // bit. This is the boot processor and the application processors are still
+    // parked, so "before every core" is simply "here".
+    _ = pcpu.armSupervisorAccessPrevention();
     // Safe this early, before the kernel is on its own page tables: the loader's
     // bootstrap tables (boot/efi.zig) map with present|writable and never set the
-    // U/S bit, so no page the BSP executes from is user-accessible.
+    // U/S bit, so no page the BSP executes from is user-accessible — and, for SMAP,
+    // no page it *reads* is either, so there is nothing for the new bit to refuse
+    // between here and the switch to the kernel's own tables.
     pcpu.initHardening();
 }
 
@@ -163,6 +170,14 @@ pub fn supervisorExecutePreventionEnabled() bool {
     return pcpu.supervisorExecutePreventionEnabled();
 }
 
+/// Whether ring 0 is barred from *reading or writing* user-mapped pages on this core
+/// (CR4.SMAP on x86_64; the privileged-access-never behaviour elsewhere). False means
+/// either the CPU doesn't offer it or the interrupt entry could not be armed to clear
+/// AC — see per-cpu.zig; the machine boots either way, unhardened and saying so.
+pub fn supervisorAccessPreventionEnabled() bool {
+    return pcpu.supervisorAccessPreventionEnabled();
+}
+
 /// Build the kernel's own page tables (with real permissions) and switch onto
 /// them. Needs the frame allocator and the boot info (for the memory map and the
 /// kernel's segment layout). Call once the frame allocator is up.