kernel: ring 0 reaches user memory only through the checked copy

SMAP makes the rule the copy layer has followed since it was written into a
rule the hardware keeps. A ring-0 read or write of a user page now faults,
so any code that reaches for a user pointer directly fails the first time it
runs rather than the first time someone attacks it — and the suite becomes
the enforcement test, because every case exercises the kernel with the bit
on. Nothing had to be fixed to turn it on, which is the retrospective proof
that the nine stragglers converted earlier were all of them.

The interrupt entry needed one instruction first. Hardware does not clear
the alignment-check flag on its way into a handler, and ring 3 sets that
flag freely, so a process could have taken an interrupt with SMAP suspended
for the duration. The system call path was already covered — its flag mask
clears it — but the interrupt path needed a `clac`, which cannot simply be
assembled in: it is an invalid instruction on a processor without SMAP, and
danos boots on those too. So the entry ships as a three-byte NOP and is
patched at boot, through the physmap, because the kernel maps its own text
read-only.

The ordering that makes that safe is enforced rather than described: the
patch sets a flag, and no core will set the SMAP bit until it is true. A
translation that fails, or bytes that read back wrong through the address
they will actually be fetched from, leave the machine unhardened and saying
so — which is the same posture the IOMMU takes, and better than enforcing
over an entry path that cannot comply. The patch runs before interrupts are
enabled and before any second core exists; a comment says so, because the
three bytes pass through an encoding that must never be executed and a
future change that moves this later has to deal with that first.

Suite 114/114, with a case that reads a user page from ring 0 and requires
the fault, and the multi-core case asserting every core that ran work had
the bit — the same shape SMEP got, for the same reason: CR4 is per-core, and
a hardening is only as wide as its narrowest core.

system/kernel/kernel.zig

@@ -288,6 +288,13 @@ fn kmain(boot_information: *const BootInformation) noreturn {
             log.write("  smep       : enabled - ring 0 cannot execute user pages\n")
         else
             log.write("  smep       : absent - ring-0 execution of user pages unprevented\n");
+        // The supervisor-access posture, the same way. Its second half is a boot-time
+        // patch (the `clac` at the interrupt entry), so "absent" here covers both a
+        // CPU without the feature and a patch that could not be applied.
+        if (architecture.supervisorAccessPreventionEnabled())
+            log.write("  smap       : enabled - ring 0 reaches user memory only through the checked copy layer\n")
+        else
+            log.write("  smap       : absent - ring-0 access to user pages unprevented\n");
         // The DMA-isolation posture, stated plainly at every boot. When a unit exists,
         // iommu.init already logged its enable block above; here we only state the
         // fail-open case, so a boot without the line is a boot with translation on.