iommu: AMD-Vi backend behind the vendor-neutral core
The second hardware backend. The IOMMU core, DMA-region capabilities, and per-device enforcement are unchanged; this adds AMD-Vi (IVRS) as an alternative to Intel VT-d (DMAR) under the same Backend vtable. - parseIvrs records the IOMMU control-register base from the first IVHD; the platform layer gains iommu_is_amd, and the core picks the backend by vendor at init. VT-d and AMD-Vi are mutually exclusive on real hardware. - iommu-amd.zig: a 2 MiB device table (every DTE zeroed = deny-all until a device is claimed), AMD native-format page tables (4 KiB leaves), a command buffer (INVALIDATE_DEVTAB_ENTRY / INVALIDATE_IOMMU_PAGES / COMPLETION_WAIT) and an event log for faults. The DTE forwards interrupts unmapped, so MSI passthrough works exactly as on VT-d. - The boot log and the iommu self-test are now vendor-aware. **UNTESTED on real AMD hardware** — danos is developed on Intel, so this is validated only against QEMU's amd-iommu, and every log line and doc says so. QEMU quirk handled: its amd-iommu does not observe the COMPLETION_WAIT store form, but consumes the command ring synchronously on the tail-register write, so invalidations are already applied by the time we poll — the backend warns once and proceeds. Cases: amd-iommu (detection + scratch-domain walker) and amd-iommu-usb-storage (full storage stack through AMD device-table translation with per-grant capabilities), both green. 106/106. This completes the IOVA/IOMMU-enforcement track: per-device DMA domains on both vendors, with buffers reachable only through delegated capabilities.
This commit is contained in:
Daniel Samson
parent
4e7cbc9792
commit
6a687fbc2b
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@ -99,9 +99,12 @@ pub const PlatformInformation = struct {
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/// and the kernel says so at every boot (the fail-open platform log line). When
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/// true, the IOMMU core builds per-device translation domains from this record.
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iommu_present: bool = false,
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/// MMIO base of the selected DMA-remapping hardware unit (the DRHD with
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/// INCLUDE_PCI_ALL — the catch-all unit covering every device not scoped to a
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/// more specific one; falls back to the first unit when none carries the flag).
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/// true when the present unit is AMD-Vi (from IVRS) rather than Intel VT-d (DMAR).
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/// The two are mutually exclusive on real hardware; the IOMMU core picks the backend.
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iommu_is_amd: bool = false,
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/// MMIO base of the selected DMA-remapping hardware unit — the VT-d DRHD with
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/// INCLUDE_PCI_ALL (the catch-all unit; falls back to the first), or the AMD-Vi
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/// IOMMU's control-register base from the first IVHD.
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iommu_base: u64 = 0,
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/// The unit's Version register (offset 0x00) — its low byte is major.minor;
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/// reading it back nonzero confirms a real, mappable VT-d unit.
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@ -279,6 +282,8 @@ const SLIT: [4]u8 = "SLIT".*;
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const SRAT: [4]u8 = "SRAT".*;
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/// Secondary System Description Table (SSDT)
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const DMAR: [4]u8 = "DMAR".*;
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/// I/O Virtualization Reporting Structure (IVRS) — the AMD-Vi analogue of DMAR.
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const IVRS: [4]u8 = "IVRS".*;
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const SSDT: [4]u8 = "SSDT".*;
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/// Serial Port Console Redirection table (SPCR) — the firmware's console UART.
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const SPCR: [4]u8 = "SPCR".*;
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@ -498,6 +503,8 @@ fn handleTable(device_tree: *DeviceTree, hal: Hal, sdt_physical: u64) !void {
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parseSpcr(header);
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} else if (std.mem.eql(u8, &sig, &DMAR)) {
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parseDmar(hal, header);
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} else if (std.mem.eql(u8, &sig, &IVRS)) {
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parseIvrs(header);
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} else if (std.mem.eql(u8, &sig, &SSDT)) {
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// Secondary namespace bytecode — collect it to publish for the ring-3 parse.
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addAmlBlock(sdt_physical);
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@ -885,6 +892,40 @@ fn parseRmrr(base: [*]align(1) const u8, total: usize, off: usize, length: usize
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}
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}
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// IVRS layout (AMD I/O Virtualization spec): 36-byte ACPI header, IVinfo u32 @36,
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// 8 reserved @40, then IVHD/IVMD blocks from @48. An IVHD common header is type u8 @0,
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// flags u8 @1, length u16 @2, device id u16 @4, capability offset u16 @6, IOMMU base
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// address u64 @8, PCI segment u16 @16, IOMMU info u16 @18.
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const ivrs_blocks_offset = 48;
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const ivhd_type_10: u8 = 0x10;
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const ivhd_type_11: u8 = 0x11;
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const ivhd_base_offset = 8;
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/// IVRS -> detect an AMD-Vi IOMMU. Record the control-register base from the first IVHD
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/// of type 0x10/0x11. Per-device entries and IVMD (the AMD analogue of RMRR) are ignored
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/// in v1 — the default-deny device table is what we build anyway, and QEMU emits no IVMD;
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/// a real machine that needs them is flagged untested on AMD regardless.
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fn parseIvrs(header: *const SystemDescriptorTableHeader) void {
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const base: [*]align(1) const u8 = @ptrCast(header);
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const total: usize = header.length;
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var off: usize = ivrs_blocks_offset;
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while (off + 4 <= total) {
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const kind = fadt(u8, base, total, off) orelse break;
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const length = fadt(u16, base, total, off + 2) orelse break;
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if (length < 4 or off + length > total) break;
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if (kind == ivhd_type_10 or kind == ivhd_type_11) {
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const iommu_base = fadt(u64, base, total, off + ivhd_base_offset) orelse 0;
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if (iommu_base != 0) {
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platform_information.iommu_present = true;
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platform_information.iommu_is_amd = true;
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platform_information.iommu_base = iommu_base;
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return; // first IVHD is enough; multi-unit is future work
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}
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}
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off += length;
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}
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}
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// --- helpers ----------------------------------------------------------------
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/// Sum `len` bytes; an ACPI table/pointer is valid when the low 8 bits are zero.
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@ -0,0 +1,259 @@
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//! system/kernel/iommu-amd.zig — AMD-Vi (AMD I/O Virtualization) backend for the IOMMU
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//! core. The AMD analogue of iommu-intel.zig: it supplies the core's `Backend` vtable
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//! with AMD-Vi's page-table entry bits and drives the device table, command buffer, and
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//! event log.
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//!
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//! **UNTESTED on real AMD hardware.** danos is developed on Intel; this backend is
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//! validated only against QEMU's `-device amd-iommu,dma-remap=on`, whose AMD-Vi
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//! emulation is far less exercised than its Intel one. Every code path here should be
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//! read as "QEMU-verified, real-AMD-unverified" until an AMD machine confirms it.
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//!
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//! Interrupt remapping is left off (the DTE forwards interrupts unmapped), so MSI writes
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//! to the 0xFEE00000 range reach the APIC untranslated, exactly as on the Intel path.
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const std = @import("std");
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const abi = @import("abi");
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const boot_handoff = @import("boot-handoff");
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const pmm = @import("pmm.zig");
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const platform = @import("platform");
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const architecture = @import("architecture");
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const log = @import("log.zig");
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const iommu = @import("iommu.zig");
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const page_size = abi.page_size;
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// MMIO register offsets from the IOMMU control-register base.
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const reg_device_table_base = 0x00; // base | (pages-1) in bits 8:0
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const reg_command_buffer_base = 0x08; // base | (ComLen << 56)
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const reg_event_log_base = 0x10; // base | (EventLen << 56)
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const reg_control = 0x18;
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const reg_command_head = 0x2000;
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const reg_command_tail = 0x2008;
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const reg_event_head = 0x2010;
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const reg_event_tail = 0x2018;
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const reg_status = 0x2020;
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const control_iommu_enable: u64 = 1 << 0;
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const control_event_log_enable: u64 = 1 << 2;
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const control_command_buffer_enable: u64 = 1 << 12;
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// Device table: one 32-byte DTE (4 qwords) per requester id, indexed by bdf.
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const device_table_pages = 512; // 2 MiB = 65536 entries (a full 256-bus segment)
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const dte_qwords = 4;
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const dte_valid: u64 = 1 << 0; // V
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const dte_translation_valid: u64 = 1 << 1; // TV
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const dte_mode_shift = 9; // bits 11:9 — page-table levels
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const dte_read: u64 = 1 << 61; // IR
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const dte_write: u64 = 1 << 62; // IW
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const dte_intctl_forward: u64 = @as(u64, 1) << 60; // qword2 bits 61:60 = 01b: forward interrupts unmapped
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// Page-table entry bits (AMD native format).
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const pte_present: u64 = 1 << 0; // PR
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const pte_next_level_shift = 9; // bits 11:9: 0 = leaf, N = pointer to a level-N table
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const pte_read: u64 = 1 << 61; // IR
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const pte_write: u64 = 1 << 62; // IW
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const address_mask: u64 = 0x000F_FFFF_FFFF_F000;
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// Command buffer / event log: one 4 KiB frame each = 256 entries.
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const ring_entries = 256;
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const ring_length_code: u64 = 8; // log2(256), the ComLen/EventLen field value
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const command_opcode_shift = 60; // opcode in bits 63:60 of qword 0
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const command_completion_wait: u64 = 0x01;
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const command_invalidate_devtab: u64 = 0x02;
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const command_invalidate_pages: u64 = 0x03;
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const completion_wait_store: u64 = 1 << 1; // S: store `data` to the supplied address
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const invalidate_pages_all: u64 = 0x000F_FFFF_FFFF_F000 | 1; // address bits 51:12 all-ones + S
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const levels: u8 = 4; // 48-bit IOVA, matching the Intel 4-level path
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var register_base: usize = 0;
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var device_table: u64 = 0; // physical base of the device table
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var command_buffer: u64 = 0;
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var event_log: u64 = 0;
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var completion_frame: u64 = 0; // COMPLETION_WAIT store target
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var command_tail: u32 = 0; // our software copy of the command tail (bytes)
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var fault_log_budget: u32 = 32;
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var completion_warned = false;
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fn read64(offset: usize) u64 {
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return @as(*const volatile u64, @ptrFromInt(register_base + offset)).*;
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}
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fn write64(offset: usize, value: u64) void {
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@as(*volatile u64, @ptrFromInt(register_base + offset)).* = value;
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}
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fn ram(physical: u64) [*]volatile u64 {
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return @ptrFromInt(boot_handoff.physicalToVirtual(physical));
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}
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/// Map the register window, allocate the device table / command buffer / event log.
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/// Returns the vtable, or null if the boot-time allocations fail.
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pub fn detect(info: platform.PlatformInformation) ?iommu.Backend {
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register_base = architecture.mapMmio(info.iommu_base, 16 * 1024, true);
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device_table = pmm.allocContiguous(device_table_pages, ~@as(u64, 0)) orelse return null;
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zero(device_table, device_table_pages); // all-zero DTE = V=0 = deny every device
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command_buffer = allocZeroedFrame() orelse return null;
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event_log = allocZeroedFrame() orelse return null;
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completion_frame = allocZeroedFrame() orelse return null;
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return iommu.Backend{
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.levels = levels,
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.supports_huge_pages = false, // 4 KiB leaves only (AMD superpage encoding deferred)
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.makeLeaf = makeLeaf,
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.makeTable = makeTable,
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.isPresent = isPresent,
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.flushStructure = flushStructure,
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.attach = attach,
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.detach = detach,
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.invalidateDomain = invalidateDomain,
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.faultDrain = faultDrain,
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};
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}
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/// Program the base registers and enable translation. The device table is already
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/// zeroed (every device denied) except any entries `attach` wrote for RMRR/claimed
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/// devices, so turning translation on blocks all other DMA and logs it.
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pub fn enable() void {
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write64(reg_device_table_base, (device_table & address_mask) | (device_table_pages - 1));
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write64(reg_command_buffer_base, (command_buffer & address_mask) | (ring_length_code << 56));
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write64(reg_event_log_base, (event_log & address_mask) | (ring_length_code << 56));
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write64(reg_command_head, 0);
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write64(reg_command_tail, 0);
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write64(reg_event_head, 0);
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write64(reg_event_tail, 0);
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command_tail = 0;
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// Buffers first, then the master enable.
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write64(reg_control, control_command_buffer_enable | control_event_log_enable);
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write64(reg_control, control_command_buffer_enable | control_event_log_enable | control_iommu_enable);
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}
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// --- Backend vtable ------------------------------------------------------------------
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fn makeLeaf(physical: u64, huge: bool) u64 {
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_ = huge; // 4 KiB only
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return (physical & address_mask) | pte_present | pte_read | pte_write; // Next Level 0 = leaf
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}
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fn makeTable(table_physical: u64, level: u8) u64 {
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// This entry (at `level`) points to a table one level down; AMD's Next Level names
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// the pointed-to table's level.
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const next_level: u64 = @as(u64, level) - 1;
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return (table_physical & address_mask) | pte_present | pte_read | pte_write | (next_level << pte_next_level_shift);
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}
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fn isPresent(entry: u64) bool {
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return (entry & pte_present) != 0;
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}
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fn flushStructure(address: usize) void {
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_ = address; // AMD-Vi reads its structures coherently
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}
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fn attach(bdf: u16, domain: u16, page_table_root: u64) void {
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const dte = ram(device_table) + @as(usize, bdf) * dte_qwords;
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dte[0] = (page_table_root & address_mask) | dte_valid | dte_translation_valid |
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(@as(u64, levels) << dte_mode_shift) | dte_read | dte_write;
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dte[1] = @as(u64, domain); // DomainID in bits 15:0
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dte[2] = dte_intctl_forward; // forward interrupts unmapped (no remapping)
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dte[3] = 0;
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invalidateDevice(bdf);
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invalidateDomain(domain);
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}
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fn detach(bdf: u16) void {
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const dte = ram(device_table) + @as(usize, bdf) * dte_qwords;
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dte[0] = 0; // V=0: deny
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dte[1] = 0;
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dte[2] = 0;
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dte[3] = 0;
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invalidateDevice(bdf);
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}
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fn invalidateDomain(domain: u16) void {
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submitCommand((command_invalidate_pages << command_opcode_shift) | (@as(u64, domain) << 32), invalidate_pages_all);
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completeAndWait();
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}
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fn faultDrain() usize {
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const tail = read64(reg_event_tail) & 0xFFFF_FFF0;
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var head = read64(reg_event_head) & 0xFFFF_FFF0;
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if (head == tail) return 0;
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var seen: usize = 0;
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while (head != tail) {
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const entry = ram(event_log) + (head / 8);
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const code: u4 = @truncate(entry[0] >> command_opcode_shift);
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if (code == 0x2) { // IO_PAGE_FAULT
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const source: u16 = @truncate(entry[0]);
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logFault(source, entry[1]);
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}
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seen += 1;
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head += 16;
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if (head >= ring_entries * 16) head = 0;
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}
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write64(reg_event_head, head);
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return seen;
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}
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fn logFault(source: u16, address: u64) void {
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if (fault_log_budget == 0) return;
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fault_log_budget -= 1;
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log.print("DANOS-IOMMU-FAULT: bdf={x:0>2}:{x:0>2}.{d} addr=0x{x} reason=amd-io-page-fault\n", .{
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source >> 8,
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(source >> 3) & 0x1F,
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source & 0x7,
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address,
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});
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if (fault_log_budget == 0) log.write("DANOS-IOMMU-FAULT: (further faults suppressed)\n");
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}
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// --- command ring --------------------------------------------------------------------
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fn invalidateDevice(bdf: u16) void {
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submitCommand((command_invalidate_devtab << command_opcode_shift) | @as(u64, bdf), 0);
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completeAndWait();
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}
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/// Append a 128-bit command (two qwords) to the ring and advance the tail.
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fn submitCommand(qword0: u64, qword1: u64) void {
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const slot = ram(command_buffer) + (command_tail / 8);
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slot[0] = qword0;
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slot[1] = qword1;
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command_tail += 16;
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if (command_tail >= ring_entries * 16) command_tail = 0;
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write64(reg_command_tail, command_tail);
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}
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/// Append a COMPLETION_WAIT (store form) and spin until the IOMMU writes our sentinel to
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/// the completion frame. QEMU consumes the command buffer synchronously on the tail-
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/// register write, so by the time we poll the prior invalidation is already applied; the
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/// store confirmation is belt-and-suspenders for real hardware. If it never lands
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/// (QEMU's amd-iommu does not implement the store form), warn ONCE and proceed — the
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/// invalidation itself has happened.
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fn completeAndWait() void {
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const sentinel: u64 = 0xC0FFEE;
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ram(completion_frame)[0] = 0;
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submitCommand(
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(command_completion_wait << command_opcode_shift) | (completion_frame & 0x000F_FFFF_FFFF_FFF8) | completion_wait_store,
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sentinel,
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);
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var spins: u64 = 0;
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while (@as(*const volatile u64, @ptrFromInt(boot_handoff.physicalToVirtual(completion_frame))).* != sentinel) {
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spins += 1;
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if (spins > 100_000) {
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if (!completion_warned) {
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completion_warned = true;
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log.write("/system/kernel: AMD-Vi COMPLETION_WAIT store not observed — proceeding (QEMU processes commands synchronously)\n");
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}
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return;
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}
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}
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}
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fn allocZeroedFrame() ?u64 {
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const frame = pmm.alloc() orelse return null;
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zero(frame, 1);
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return frame;
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}
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fn zero(physical: u64, pages: usize) void {
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const words = ram(physical);
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var i: usize = 0;
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while (i < pages * page_size / 8) : (i += 1) words[i] = 0;
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}
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@ -32,6 +32,7 @@ const platform = @import("platform");
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const devices_broker = @import("devices-broker.zig");
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const log = @import("log.zig");
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const intel = @import("iommu-intel.zig");
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const amd = @import("iommu-amd.zig");
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const page_size: u64 = abi.page_size;
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const page_mask: u64 = page_size - 1;
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@ -104,8 +105,18 @@ pub fn init() void {
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kind = .none;
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return;
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}
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// Only Intel VT-d for now; AMD-Vi (iommu-amd.zig) selects here when its detection
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// (IVRS) lands. A present-but-unsupported unit stays fail-open with a logged reason.
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// Pick the backend by vendor. A present-but-unusable unit stays fail-open with a
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// logged reason rather than half-enabling.
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if (info.iommu_is_amd) {
|
||||
if (amd.detect(info)) |be| {
|
||||
backend = be;
|
||||
kind = .amd_vi;
|
||||
} else {
|
||||
kind = .none;
|
||||
log.write("/system/kernel: WARNING AMD-Vi present but unusable — staying fail-open\n");
|
||||
return;
|
||||
}
|
||||
} else {
|
||||
if (intel.detect(info)) |be| {
|
||||
backend = be;
|
||||
kind = .intel_vtd;
|
||||
|
|
@ -114,12 +125,12 @@ pub fn init() void {
|
|||
log.write("/system/kernel: WARNING IOMMU present but unusable — staying fail-open\n");
|
||||
return;
|
||||
}
|
||||
}
|
||||
|
||||
// The root table starts empty: every device's context entry is not-present, so any
|
||||
// DMA faults until the device's driver claims it (confineDevice gives it a private
|
||||
// domain). PCI functions are enumerated post-boot by the ring-3 pci-bus driver, so
|
||||
// there is nothing to attach at init anyway.
|
||||
intel.enable();
|
||||
// The translation structures start empty: every device is denied until its driver
|
||||
// claims it (confineDevice gives it a private domain). PCI functions are enumerated
|
||||
// post-boot by the ring-3 pci-bus driver, so there is nothing to attach at init.
|
||||
if (kind == .amd_vi) amd.enable() else intel.enable();
|
||||
logEnabled(info);
|
||||
}
|
||||
|
||||
|
|
@ -421,6 +432,11 @@ fn hardwareId(domain: u16) u16 {
|
|||
}
|
||||
|
||||
fn logEnabled(info: platform.PlatformInformation) void {
|
||||
if (kind == .amd_vi) {
|
||||
log.write("/system/kernel: iommu online (AMD-Vi) — UNTESTED on real AMD hardware (QEMU-verified only)\n");
|
||||
log.print(" levels : {d} (48-bit)\n", .{backend.levels});
|
||||
return;
|
||||
}
|
||||
log.write("/system/kernel: iommu online (Intel VT-d)\n");
|
||||
log.print(" version : 0x{x}\n", .{info.iommu_version});
|
||||
log.print(" agaw : {d} levels\n", .{backend.levels});
|
||||
|
|
|
|||
|
|
@ -1251,8 +1251,11 @@ fn msiTest() void {
|
|||
fn iommuTest() void {
|
||||
log("DANOS-TEST-BEGIN: iommu\n", .{});
|
||||
const pinfo = platform.platformInformation();
|
||||
check("IOMMU found in the DMAR table", pinfo.iommu_present);
|
||||
check("VT-d unit has a register base", pinfo.iommu_base != 0);
|
||||
check("IOMMU found in the firmware tables", pinfo.iommu_present);
|
||||
check("IOMMU unit has a register base", pinfo.iommu_base != 0);
|
||||
// The VT-d version register is a live-unit sanity check; AMD-Vi (from IVRS) records
|
||||
// no version, so gate it on the vendor.
|
||||
if (!pinfo.iommu_is_amd)
|
||||
check("VT-d version register reads back nonzero (real, mappable unit)", pinfo.iommu_version != 0);
|
||||
log("DANOS-IOMMU: base=0x{x} version=0x{x} capabilities=0x{x}\n", .{ pinfo.iommu_base, pinfo.iommu_version, pinfo.iommu_capabilities });
|
||||
|
||||
|
|
|
|||
|
|
@ -193,6 +193,23 @@ CASES = [
|
|||
"qemu_extra": ["-device", "intel-iommu,intremap=off", "-device", "e1000e"],
|
||||
"expect": r"(?s)(?=.*DANOS-IOMMU-FAULT: bdf=)(?=.*iommu-fault-test: system alive)(?=.*DANOS-TEST-RESULT: PASS)",
|
||||
"fail": r"iommu-fault-test: FAIL|DANOS-TEST-RESULT: FAIL|CPU EXCEPTION|KERNEL PANIC"},
|
||||
# AMD-Vi: the same detection + scratch-domain walker proof as the `iommu` case, but on
|
||||
# the AMD backend (IVRS parse, device table, command buffer). QEMU's amd-iommu needs
|
||||
# dma-remap=on (default off = translation silently ignored). UNTESTED on real AMD.
|
||||
{"name": "amd-iommu",
|
||||
"build_case": "iommu",
|
||||
"qemu_extra": ["-device", "amd-iommu,dma-remap=on,intremap=off"],
|
||||
"expect": r"(?s)(?=.*iommu online \(AMD-Vi\))(?=.*DANOS-IOMMU: enabled base=0x[0-9a-f]+ domains active)(?=.*DANOS-TEST-RESULT: PASS)",
|
||||
"fail": r"DANOS-TEST-RESULT: FAIL|DANOS-IOMMU-FAULT"},
|
||||
# DMA under AMD-Vi translation: the full USB storage stack through AMD device-table
|
||||
# translation. Tentative — land depends on QEMU amd-iommu behaving. UNTESTED on real AMD.
|
||||
{"name": "amd-iommu-usb-storage",
|
||||
"build_case": "fat-mount",
|
||||
"smp": 4,
|
||||
"timeout": 150,
|
||||
"qemu_extra": ["-device", "amd-iommu,dma-remap=on,intremap=off"],
|
||||
"expect": r"(?s)(?=.*iommu online \(AMD-Vi\))(?=.*fat: mounted /mnt/usb)(?=.*fat-test: ok)",
|
||||
"fail": r"DANOS-TEST-RESULT: FAIL|DANOS-IOMMU-FAULT"},
|
||||
# Port I/O grants: a claimed device's io_port resource lets a driver read/write its
|
||||
# ports (PS/2 status 0x64), gated by the claim; out-of-range/unclaimed is refused.
|
||||
{"name": "ioport",
|
||||
|
|
|
|||
Loading…
Reference in New Issue