virtio-gpu: a modern virtio 1.0 display driver, bring-up to a flushed frame (v2 V3)
The first native scanout backend's driver half. The device manager matches the
virtio-gpu PCI function by its Display/Other class triple and spawns the driver,
which claims the device, confirms vendor 0x1AF4/device 0x1050 from config space,
enables memory-space + bus mastering, and walks the virtio vendor capabilities to
find the common-config and notify structures in its BAR.
From there it is the standard modern-virtio bring-up: reset, negotiate VERSION_1,
stand up the control virtqueue in coherent DMA, then drive the GPU end to end —
RESOURCE_CREATE_2D, ATTACH_BACKING (a coherent DMA buffer; V4 swaps in the shm-
shared surface), SET_SCANOUT, paint a known pattern, TRANSFER_TO_HOST_2D,
RESOURCE_FLUSH, and wait for the device's used-ring ack. Reading the backing back
proves it is CPU-visible RAM; the ack proves the device consumed the frame —
together the automated stand-in for "it's on screen", no screenshot.
- system/drivers/virtio-gpu/: the driver, plus virtio-gpu-protocol.zig (control
commands) and virtio-pci.zig (the 1.0 PCI transport + split-virtqueue), both with
host-tested struct sizes.
- device-manager matches the display/other class triple to "virtio-gpu"; the driver
self-confirms the vendor/device id, since the class alone cannot distinguish it.
- ServiceId.scanout (11): the driver registers it so the compositor finds it in V4.
Gate: python3 test/qemu_test.py virtio-gpu (QEMU -device virtio-gpu-pci) — the
device-manager stack discovers the function, the driver brings up a 640x480 scanout
and flushes a test pattern: "virtio-gpu: scanout 640x480 online" + "flush acked,
pixel check ok". host tests, display-service, shm, and device-list still pass.
Note: the pre-existing pci-scan case triple-faults on main (verified at 88ad432,
before this change); it is unrelated and tracked separately.
This commit is contained in:
Daniel Samson
@@ -0,0 +1,443 @@
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//! /system/drivers/virtio-gpu — the virtio-gpu (virtio 1.0, modern PCI) display driver.
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//! The device manager spawns it for the display/other PCI function (class 0x0380) whose
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//! config space says vendor 0x1AF4 / device 0x1050; this instance claims that device and
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//! brings up a single 2D scanout.
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//!
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//! V3 (this increment): the whole path end to end, proven from serial without a screenshot.
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//! Claim the function, map its config space (resource 0) and the BAR that carries the
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//! virtio structures, walk the vendor capabilities to find common-config / notify, reset
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//! and negotiate VERSION_1, stand up the control virtqueue in DMA memory, then drive the
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//! GPU: RESOURCE_CREATE_2D → ATTACH_BACKING (a coherent DMA buffer) → SET_SCANOUT, paint a
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//! known test pattern, TRANSFER_TO_HOST_2D → RESOURCE_FLUSH, and **wait for the device's
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//! used-ring ack**. Reading the backing back confirms it is CPU-visible; the ack confirms
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//! the device consumed the frame. The compositor backend, hot-attach, mode-set/EDID, and
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//! restart/re-attach are V4–V6. See docs/display-v2.md.
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const std = @import("std");
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const runtime = @import("runtime");
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const mmio = @import("mmio");
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const device = runtime.device;
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const dma = runtime.dma;
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const system = runtime.system;
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const ipc = runtime.ipc;
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const vp = @import("virtio-pci.zig");
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const vg = @import("virtio-gpu-protocol.zig");
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/// The PCI vendor/device ids of a modern virtio-gpu (Red Hat / virtio; GPU is a
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/// virtio-1.0-only device, so the id is always the modern 0x1050 — no legacy variant).
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const virtio_vendor: u16 = 0x1AF4;
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const virtio_gpu_device: u16 = 0x1050;
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/// The scanout we bring up. A modest, fixed geometry for V3 (mode-set from the EDID is V5)
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/// — kept small so the backing is an easy contiguous DMA run.
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const scanout_width: u32 = 640;
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const scanout_height: u32 = 480;
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const scanout_bytes: usize = @as(usize, scanout_width) * scanout_height * 4;
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const resource_id: u32 = 1;
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/// The control virtqueue. We drive it synchronously — one command, notify, poll the used
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/// ring — so a depth of 16 is ample; we ask the device to shrink to it (virtio 1.0 lets the
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/// driver reduce queue_size), keeping the whole ring inside one page.
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const queue_size: u16 = 16;
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const desc_offset: usize = 0; // 16 * 16 = 256 bytes
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const avail_offset: usize = 256; // flags + idx + ring[16] + used_event = 38 bytes
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const used_offset: usize = 1024; // flags + idx + ring[16] + avail_event = 134 bytes
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/// The command scratch: the request the device reads, then its response, in one DMA page.
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const request_offset: usize = 0;
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const response_offset: usize = 2048;
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var device_id: u64 = 0;
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// Mapped virtio structures (virtual addresses into the device's BAR).
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var common_base: usize = 0;
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var notify_base: usize = 0;
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var notify_multiplier: u32 = 0;
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var notify_addr: usize = 0;
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// Per-BAR mapping cache: several capabilities usually share one BAR, and mmio_map must not
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// be asked to map the same resource twice.
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var bar_virtual: [6]usize = .{ 0, 0, 0, 0, 0, 0 };
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// DMA memory: the virtqueue rings, the command scratch, and the scanout backing.
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var ring: dma.Region = undefined;
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var command: dma.Region = undefined;
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var backing: dma.Region = undefined;
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// Split-virtqueue producer/consumer shadows.
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var avail_shadow: u16 = 0;
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var used_shadow: u16 = 0;
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/// Format one whole log line and emit it in a single `write`, so this driver's output can
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/// never interleave mid-line with the other drivers the manager runs concurrently.
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fn log(comptime fmt: []const u8, arguments: anytype) void {
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var line: [160]u8 = undefined;
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_ = system.write(std.fmt.bufPrint(&line, fmt, arguments) catch return);
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}
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// --- common-config register access (little-endian MMIO at `common_base`) ---------------
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fn cfgRead(comptime T: type, comptime field: []const u8) T {
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return mmio.read(T, common_base + @offsetOf(vp.CommonCfg, field));
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}
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fn cfgWrite(comptime T: type, comptime field: []const u8, value: T) void {
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mmio.write(T, common_base + @offsetOf(vp.CommonCfg, field), value);
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}
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/// Write a 64-bit common-config register as two 32-bit halves (low then high) — the widest
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/// access every virtio-pci host is required to accept for the queue-address registers.
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fn cfgWrite64(comptime field: []const u8, value: u64) void {
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const at = common_base + @offsetOf(vp.CommonCfg, field);
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mmio.write(u32, at, @truncate(value));
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mmio.write(u32, at + 4, @truncate(value >> 32));
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}
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fn orStatus(bit: u8) void {
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cfgWrite(u8, "device_status", cfgRead(u8, "device_status") | bit);
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}
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// --- PCI config-space capability walk (config space is resource 0) ---------------------
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/// Map the BAR numbered `bar` (0..5) and return its virtual base, correlating the BAR's
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/// physical address (read from config space) with one of our device resources — because a
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/// virtio capability names a BAR *number*, while `mmio_map` takes a *resource index* (and
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/// resource 0 is config space, so BAR resources are re-numbered and gaps skipped).
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fn mapBar(config: usize, descriptor: *const device.DeviceDescriptor, bar: u8) ?usize {
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if (bar >= 6) return null;
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if (bar_virtual[bar] != 0) return bar_virtual[bar];
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const low = mmio.read(u32, config + 0x10 + @as(usize, bar) * 4);
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if (low & 0x1 != 0) return null; // an I/O-space BAR — virtio structures are in memory BARs
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var base: u64 = low & 0xFFFF_FFF0;
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if ((low & 0x6) == 0x4) { // 64-bit memory BAR: the high half is the next dword
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const high = mmio.read(u32, config + 0x10 + (@as(usize, bar) + 1) * 4);
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base |= @as(u64, high) << 32;
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}
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for (descriptor.resources[0..@intCast(descriptor.resource_count)], 0..) |resource, index| {
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if (resource.kind == @intFromEnum(device.ResourceKind.memory) and resource.start == base) {
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const v = device.mmioMap(device_id, index) orelse return null;
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bar_virtual[bar] = v;
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return v;
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}
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}
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log("virtio-gpu: BAR {d} (physical 0x{x}) is not a mapped resource\n", .{ bar, base });
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return null;
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}
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/// Walk the PCI capability list from mapped config space, recording the common-config and
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/// notify structures (the only two V3 needs). Returns false if either is missing.
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fn walkCapabilities(config: usize, descriptor: *const device.DeviceDescriptor) bool {
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if (mmio.read(u16, config + 0x06) & 0x10 == 0) { // Status bit 4: capabilities list present
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log("virtio-gpu: device has no PCI capability list\n", .{});
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return false;
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}
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var cap: u8 = @as(u8, @truncate(mmio.read(u8, config + 0x34))) & 0xFC;
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var guard: u32 = 0;
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while (cap != 0 and guard < 48) : (guard += 1) {
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const at = config + cap;
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const id = mmio.read(u8, at + 0);
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const next = mmio.read(u8, at + 1) & 0xFC;
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// Only map BARs for the structures V3 uses (common + notify). The other virtio
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// capabilities (isr, device, and especially the cfg_pci back-door, which carries a
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// placeholder bar=0/offset=0) reference BARs we never touch, so mapping them would
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// just log spurious "not a mapped resource" noise.
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if (id == vp.pci_cap_vendor) {
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const cfg_type = mmio.read(u8, at + 3);
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if (cfg_type == vp.cfg_common or cfg_type == vp.cfg_notify) {
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const bar = mmio.read(u8, at + 4);
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const offset = mmio.read(u32, at + 8);
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if (mapBar(config, descriptor, bar)) |bar_base| {
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if (cfg_type == vp.cfg_common) {
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common_base = bar_base + offset;
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} else {
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notify_base = bar_base + offset;
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notify_multiplier = mmio.read(u32, at + 16); // virtio_pci_notify_cap tail
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}
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}
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}
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}
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cap = next;
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}
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if (common_base == 0 or notify_base == 0) {
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log("virtio-gpu: missing common-config or notify capability\n", .{});
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return false;
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}
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return true;
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}
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// --- the control virtqueue -------------------------------------------------------------
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/// Publish the two-descriptor chain (request read by the device, response written by it),
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/// notify the control queue, and wait for the device to return the buffer on the used ring.
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fn submit(request_len: usize, response_len: usize) bool {
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const desc: [*]vp.Desc = @ptrFromInt(ring.virtual + desc_offset);
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desc[0] = .{
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.addr = command.physical + request_offset,
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.len = @intCast(request_len),
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.flags = vp.desc_flag_next,
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.next = 1,
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};
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desc[1] = .{
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.addr = command.physical + response_offset,
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.len = @intCast(response_len),
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.flags = vp.desc_flag_write,
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.next = 0,
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};
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const avail_ring: [*]u16 = @ptrFromInt(ring.virtual + avail_offset + 4);
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avail_ring[avail_shadow % queue_size] = 0; // head of the chain is descriptor 0
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mmio.wmb();
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avail_shadow +%= 1;
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mmio.write(u16, ring.virtual + avail_offset + 2, avail_shadow); // avail.idx
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mmio.wmb();
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mmio.write(u16, notify_addr, 0); // ring the control queue's doorbell
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return waitUsed();
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}
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/// Spin, then sleep-poll, on the used-ring index until the device advances it. QEMU
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/// processes the notify on its own thread, so the ack usually lands immediately; the sleep
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/// fallback covers a device that defers it without burning the CPU.
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fn waitUsed() bool {
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var tries: u32 = 0;
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while (tries < 2000) : (tries += 1) {
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mmio.rmb();
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const idx = mmio.read(u16, ring.virtual + used_offset + 2); // used.idx
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if (idx != used_shadow) {
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used_shadow = idx;
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return true;
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}
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if (tries > 8) system.sleep(1);
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}
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return false;
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}
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/// The type field of the response the device wrote — `resp_ok_nodata` on success.
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fn responseType() u32 {
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const response: *vg.CtrlHdr = @ptrFromInt(command.virtual + response_offset);
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return response.type;
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}
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/// Submit a command whose response is a bare header, returning its response type (0 if the
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/// device never acked).
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fn command_nodata(request_len: usize) u32 {
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if (!submit(request_len, @sizeOf(vg.CtrlHdr))) return 0;
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return responseType();
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}
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const ok_nodata: u32 = @intFromEnum(vg.CmdType.resp_ok_nodata);
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fn requestAt(comptime T: type) *T {
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return @ptrFromInt(command.virtual + request_offset);
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}
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/// A deterministic, recognisable pixel so a read-back is a real check, not a tautology.
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fn testPixel(index: u32) u32 {
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return 0xFF00_0000 | (index *% 0x9E37_79B1);
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}
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// --- bring-up --------------------------------------------------------------------------
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fn initialise(endpoint: ipc.Handle) bool {
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_ = endpoint;
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if (!device.claim(device_id)) {
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log("virtio-gpu: unable to claim device {d}\n", .{device_id});
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return false;
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}
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var descriptors: [64]device.DeviceDescriptor = undefined;
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const total = device.enumerate(&descriptors);
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const descriptor = for (descriptors[0..@min(total, descriptors.len)]) |*d| {
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if (d.id == device_id) break d;
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} else {
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log("virtio-gpu: device {d} not in the device tree\n", .{device_id});
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return false;
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};
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// Config space is resource 0. Confirm it really is a virtio-gpu, then enable memory-space
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// decode + bus mastering (the device DMAs the ring and backing out of RAM); pci-bus only
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// preserves whatever the firmware left, and a secondary display is often left disabled.
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const config = device.mmioMap(device_id, 0) orelse {
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log("virtio-gpu: config-space map failed\n", .{});
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return false;
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};
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const vendor = mmio.read(u16, config + 0x00);
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const dev = mmio.read(u16, config + 0x02);
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if (vendor != virtio_vendor or dev != virtio_gpu_device) {
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log("virtio-gpu: not a virtio-gpu (vendor 0x{x} device 0x{x})\n", .{ vendor, dev });
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return false;
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}
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mmio.write(u16, config + 0x04, mmio.read(u16, config + 0x04) | 0x06); // MEM + bus master
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if (!walkCapabilities(config, descriptor)) return false;
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// Reset, then the modern feature handshake: acknowledge, take driver ownership, require
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// VERSION_1 and offer nothing else, and confirm the device accepts that.
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cfgWrite(u8, "device_status", 0);
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orStatus(vp.status_acknowledge);
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orStatus(vp.status_driver);
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cfgWrite(u32, "device_feature_select", vp.feature_version_1_word);
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if (cfgRead(u32, "device_feature") & vp.feature_version_1_bit == 0) {
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log("virtio-gpu: device does not offer VERSION_1 (not a modern device)\n", .{});
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return false;
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}
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cfgWrite(u32, "driver_feature_select", 0);
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cfgWrite(u32, "driver_feature", 0);
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cfgWrite(u32, "driver_feature_select", vp.feature_version_1_word);
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cfgWrite(u32, "driver_feature", vp.feature_version_1_bit);
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orStatus(vp.status_features_ok);
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if (cfgRead(u8, "device_status") & vp.status_features_ok == 0) {
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log("virtio-gpu: device rejected the negotiated features\n", .{});
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return false;
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}
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// Stand up the control virtqueue (queue 0) in coherent DMA memory.
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cfgWrite(u16, "queue_select", 0);
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const device_qsize = cfgRead(u16, "queue_size");
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if (device_qsize < queue_size) {
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log("virtio-gpu: control queue too small ({d})\n", .{device_qsize});
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return false;
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}
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ring = dma.alloc(4096, dma.coherent) orelse {
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log("virtio-gpu: virtqueue allocation failed\n", .{});
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return false;
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};
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command = dma.alloc(4096, dma.coherent) orelse {
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log("virtio-gpu: command-buffer allocation failed\n", .{});
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return false;
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};
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mmio.write(u16, ring.virtual + avail_offset, 1); // VIRTQ_AVAIL_F_NO_INTERRUPT: we poll
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cfgWrite(u16, "queue_size", queue_size);
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cfgWrite64("queue_desc", ring.physical + desc_offset);
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cfgWrite64("queue_driver", ring.physical + avail_offset);
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cfgWrite64("queue_device", ring.physical + used_offset);
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cfgWrite(u16, "queue_msix_vector", 0xFFFF); // VIRTIO_MSI_NO_VECTOR
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cfgWrite(u16, "queue_enable", 1);
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cfgWrite(u16, "queue_select", 0);
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notify_addr = notify_base + @as(usize, cfgRead(u16, "queue_notify_off")) * notify_multiplier;
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orStatus(vp.status_driver_ok);
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// Drive the GPU: create a 2D resource, back it with DMA memory, and make it scanout 0.
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{
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const request = requestAt(vg.ResourceCreate2d);
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request.* = .{
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.hdr = .{ .type = @intFromEnum(vg.CmdType.resource_create_2d) },
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.resource_id = resource_id,
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.format = vg.format_b8g8r8x8_unorm,
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.width = scanout_width,
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.height = scanout_height,
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};
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if (command_nodata(@sizeOf(vg.ResourceCreate2d)) != ok_nodata) {
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log("virtio-gpu: resource_create_2d failed\n", .{});
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return false;
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}
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}
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backing = dma.alloc(scanout_bytes, dma.coherent) orelse {
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log("virtio-gpu: scanout backing allocation failed\n", .{});
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return false;
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};
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{
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const request = requestAt(vg.ResourceAttachBacking);
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request.* = .{
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.hdr = .{ .type = @intFromEnum(vg.CmdType.resource_attach_backing) },
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.resource_id = resource_id,
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.nr_entries = 1,
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};
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const entry: *vg.MemEntry = @ptrFromInt(command.virtual + request_offset + @sizeOf(vg.ResourceAttachBacking));
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entry.* = .{ .addr = backing.physical, .length = @intCast(scanout_bytes) };
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if (command_nodata(@sizeOf(vg.ResourceAttachBacking) + @sizeOf(vg.MemEntry)) != ok_nodata) {
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log("virtio-gpu: resource_attach_backing failed\n", .{});
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return false;
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}
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}
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{
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const request = requestAt(vg.SetScanout);
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request.* = .{
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.hdr = .{ .type = @intFromEnum(vg.CmdType.set_scanout) },
|
||||
.rect = .{ .x = 0, .y = 0, .width = scanout_width, .height = scanout_height },
|
||||
.scanout_id = 0,
|
||||
.resource_id = resource_id,
|
||||
};
|
||||
if (command_nodata(@sizeOf(vg.SetScanout)) != ok_nodata) {
|
||||
log("virtio-gpu: set_scanout failed\n", .{});
|
||||
return false;
|
||||
}
|
||||
}
|
||||
log("virtio-gpu: scanout {d}x{d} online\n", .{ scanout_width, scanout_height });
|
||||
|
||||
// Paint a known pattern, transfer it to the host resource, and flush it to the display.
|
||||
const pixels: [*]u32 = @ptrFromInt(backing.virtual);
|
||||
const pixel_count: u32 = scanout_width * scanout_height;
|
||||
for (0..pixel_count) |i| pixels[i] = testPixel(@intCast(i));
|
||||
mmio.wmb();
|
||||
|
||||
{
|
||||
const request = requestAt(vg.TransferToHost2d);
|
||||
request.* = .{
|
||||
.hdr = .{ .type = @intFromEnum(vg.CmdType.transfer_to_host_2d) },
|
||||
.rect = .{ .x = 0, .y = 0, .width = scanout_width, .height = scanout_height },
|
||||
.offset = 0,
|
||||
.resource_id = resource_id,
|
||||
};
|
||||
if (command_nodata(@sizeOf(vg.TransferToHost2d)) != ok_nodata) {
|
||||
log("virtio-gpu: transfer_to_host_2d failed\n", .{});
|
||||
return false;
|
||||
}
|
||||
}
|
||||
{
|
||||
const request = requestAt(vg.ResourceFlush);
|
||||
request.* = .{
|
||||
.hdr = .{ .type = @intFromEnum(vg.CmdType.resource_flush) },
|
||||
.rect = .{ .x = 0, .y = 0, .width = scanout_width, .height = scanout_height },
|
||||
.resource_id = resource_id,
|
||||
};
|
||||
if (command_nodata(@sizeOf(vg.ResourceFlush)) != ok_nodata) {
|
||||
log("virtio-gpu: resource_flush was not acked\n", .{});
|
||||
return false;
|
||||
}
|
||||
}
|
||||
|
||||
// The scanout backing is CPU-visible RAM: read the pattern back to prove the mapping,
|
||||
// which together with the flush ack above is the automated stand-in for "it's on screen".
|
||||
mmio.rmb();
|
||||
if (pixels[0] != testPixel(0) or pixels[pixel_count / 2] != testPixel(pixel_count / 2)) {
|
||||
log("virtio-gpu: pixel read-back mismatch\n", .{});
|
||||
return false;
|
||||
}
|
||||
log("virtio-gpu: flush acked, pixel check ok\n", .{});
|
||||
return true;
|
||||
}
|
||||
|
||||
/// The `scanout` service exists from V3 so the compositor can find it in V4; it carries no
|
||||
/// requests yet (the ping is answered by the harness), so anything else is a no-op.
|
||||
fn onMessage(message: []const u8, reply: []u8, sender: u32, capability: ?ipc.Handle) usize {
|
||||
_ = message;
|
||||
_ = reply;
|
||||
_ = sender;
|
||||
_ = capability;
|
||||
return 0;
|
||||
}
|
||||
|
||||
pub fn main(init: runtime.process.Init) void {
|
||||
const argument = init.arguments.get(1) orelse {
|
||||
_ = system.write("virtio-gpu: missing device id (argv[1])\n");
|
||||
return;
|
||||
};
|
||||
device_id = std.fmt.parseInt(u64, argument, 10) catch {
|
||||
log("virtio-gpu: malformed device id '{s}'\n", .{argument});
|
||||
return;
|
||||
};
|
||||
runtime.service.run(256, .{
|
||||
.service = .scanout,
|
||||
.init = initialise,
|
||||
.on_message = onMessage,
|
||||
});
|
||||
}
|
||||
|
||||
pub const panic = runtime.panic;
|
||||
comptime {
|
||||
_ = &runtime.start._start; // pull the runtime entry shim into the image
|
||||
}
|
||||
Reference in New Issue
Block a user