moving kernel code to kernel/
This commit is contained in:
@@ -0,0 +1,202 @@
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//! Local APIC and its timer — the source of device interrupts.
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//!
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//! Modern x86 routes interrupts through the per-CPU Local APIC (the legacy 8259
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//! PIC is remapped out of the way and masked). The LAPIC also has a built-in
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//! timer, which is the simplest device interrupt to bring up: it needs no
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//! external routing, just a vector and a count. We use it as danos's heartbeat.
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//!
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//! The LAPIC is memory-mapped (default physical 0xFEE00000, inside our identity
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//! map). Every interrupt must be acknowledged with an end-of-interrupt write, or
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//! the LAPIC won't deliver the next one.
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const io = @import("io.zig");
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/// IDT vector the timer fires on (in the device range, >= 32).
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pub const timer_vector = 32;
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/// Spurious-interrupt vector. Low nibble 0xF by convention; also in our gate
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/// range so a stray spurious interrupt lands on a valid (no-op) handler.
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const spurious_vector = 47;
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// LAPIC register offsets.
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const reg_spurious = 0x0F0;
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const reg_eoi = 0x0B0;
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const reg_lvt_timer = 0x320;
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const reg_timer_initial = 0x380;
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const reg_timer_current = 0x390;
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const reg_timer_divide = 0x3E0;
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const lvt_masked = 1 << 16;
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const lvt_periodic = 1 << 17;
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const timer_divide_16 = 0x3;
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const ia32_apic_base_msr = 0x1B;
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/// LAPIC MMIO base. A runtime var (not a constant) both because we read it from
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/// the MSR and so register writes compile to normal stores rather than a
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/// `mov moffs`, which the self-hosted backend can't encode.
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var base: usize = 0xFEE00000;
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var tick_count: u64 = 0;
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/// LAPIC timer counts per millisecond, measured against the PIT (see calibrate).
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/// At divide-by-16, this is the effective counting rate.
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var ticks_per_ms: u32 = 0;
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/// The periodic-interrupt frequency the timer is armed at, once initTimer runs.
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var timer_hz: u32 = 0;
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/// TSC (Time Stamp Counter) calibration: cycles per second, and the count at boot.
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/// The TSC is a per-core cycle counter, giving a ~nanosecond high-resolution
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/// monotonic clock — far finer than the millisecond timer tick.
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var tsc_hz: u64 = 0;
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var tsc_base: u64 = 0;
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/// Read the 64-bit Time Stamp Counter.
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fn rdtsc() u64 {
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var low: u32 = undefined;
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var high: u32 = undefined;
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asm volatile ("rdtsc"
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: [low] "={eax}" (low),
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[high] "={edx}" (high),
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);
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return (@as(u64, high) << 32) | low;
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}
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fn read(reg: u32) u32 {
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return @as(*volatile u32, @ptrFromInt(base + reg)).*;
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}
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fn write(reg: u32, value: u32) void {
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@as(*volatile u32, @ptrFromInt(base + reg)).* = value;
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}
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/// Move the legacy 8259 PIC's vectors to 0x20-0x2F (clear of the CPU exception
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/// vectors) and mask every line, so it can't deliver interrupts behind the APIC.
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fn remapAndMaskPic() void {
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io.outb(0x20, 0x11); // start init (cascade mode)
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io.outb(0xA0, 0x11);
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io.outb(0x21, 0x20); // master offset 0x20
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io.outb(0xA1, 0x28); // slave offset 0x28
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io.outb(0x21, 0x04); // tell master about slave on IRQ2
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io.outb(0xA1, 0x02);
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io.outb(0x21, 0x01); // 8086 mode
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io.outb(0xA1, 0x01);
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io.outb(0x21, 0xFF); // mask all
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io.outb(0xA1, 0xFF);
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}
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/// Enable the Local APIC: mask the PIC, set the global-enable MSR bit, and
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/// software-enable the APIC via its spurious-vector register.
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pub fn init() void {
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remapAndMaskPic();
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const msr = io.rdmsr(ia32_apic_base_msr);
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base = @intCast(msr & 0xFFFFF000); // physical base is bits 12+
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io.wrmsr(ia32_apic_base_msr, msr | (1 << 11)); // global enable
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write(reg_spurious, 0x100 | spurious_vector); // bit 8 = software enable
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}
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/// Measure the LAPIC timer's and the TSC's rates against the PIT (channel 2, which
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/// can be polled without interrupts). We run the LAPIC timer one-shot from its max
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/// count and snapshot the TSC while the PIT counts out a known 10 ms, then see how
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/// far each got. This gives real time, which the RTOS timing guarantees depend on.
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pub fn calibrate() void {
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const pit_hz = 1_193_182;
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const calib_ms = 10;
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const pit_count: u16 = @intCast(pit_hz / 1000 * calib_ms);
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// LAPIC timer: divide 16, masked (no interrupt — we just want the count),
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// counting down from the maximum.
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write(reg_timer_divide, timer_divide_16);
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write(reg_lvt_timer, lvt_masked);
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write(reg_timer_initial, 0xFFFFFFFF);
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// PIT channel 2, mode 0 (interrupt on terminal count): load the count with the
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// gate low, then raise the gate to start it counting.
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io.outb(0x61, io.inb(0x61) & 0xFC); // speaker off, gate low
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io.outb(0x43, 0xB0); // channel 2, lo/hi byte, mode 0
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io.outb(0x42, @truncate(pit_count));
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io.outb(0x42, @truncate(pit_count >> 8));
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const tsc_start = rdtsc();
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io.outb(0x61, (io.inb(0x61) & 0xFC) | 0x01); // gate high -> start
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while (io.inb(0x61) & 0x20 == 0) {} // poll channel-2 output until terminal count
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const tsc_end = rdtsc();
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const elapsed = 0xFFFFFFFF - read(reg_timer_current);
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write(reg_timer_initial, 0); // stop the timer
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ticks_per_ms = elapsed / calib_ms;
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tsc_hz = (tsc_end -% tsc_start) * (1000 / calib_ms); // cycles/10ms -> cycles/s
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tsc_base = rdtsc(); // the clock's zero point (boot)
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}
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/// Arm the LAPIC timer to fire on `timer_vector` at `hz` (periodic). Requires
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/// calibrate() to have run.
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pub fn initTimer(hz: u32) void {
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timer_hz = hz;
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const count = @as(u64, ticks_per_ms) * 1000 / hz; // counts per (1/hz) second
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write(reg_timer_divide, timer_divide_16);
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write(reg_lvt_timer, timer_vector | lvt_periodic);
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write(reg_timer_initial, @intCast(count));
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}
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/// Configured periodic-interrupt frequency (Hz).
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pub fn frequencyHz() u32 {
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return timer_hz;
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}
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/// Measured LAPIC timer frequency (Hz), for reporting/sanity checks.
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pub fn lapicHz() u64 {
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return @as(u64, ticks_per_ms) * 1000;
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}
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/// Measured TSC frequency (Hz).
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pub fn tscHz() u64 {
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return tsc_hz;
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}
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// Monotonic high-resolution clock, from the TSC. A function per resolution, each
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// scaling the cycle delta directly at its unit (the 128-bit intermediate avoids
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// overflow across a long uptime). nanos() resolves to a few ns; millis() is what
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// the scheduler uses for sleep deadlines.
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pub fn nanos() u64 {
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if (tsc_hz == 0) return 0;
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return @intCast(@as(u128, rdtsc() -% tsc_base) * 1_000_000_000 / tsc_hz);
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}
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pub fn micros() u64 {
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if (tsc_hz == 0) return 0;
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return @intCast(@as(u128, rdtsc() -% tsc_base) * 1_000_000 / tsc_hz);
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}
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pub fn millis() u64 {
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if (tsc_hz == 0) return 0;
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return @intCast(@as(u128, rdtsc() -% tsc_base) * 1_000 / tsc_hz);
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}
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/// Acknowledge the current interrupt so the LAPIC will deliver the next one.
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pub fn eoi() void {
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write(reg_eoi, 0);
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}
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/// Optional callback run each tick (the scheduler registers it for preemption).
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var on_tick: ?*const fn () void = null;
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pub fn setTickHook(hook: *const fn () void) void {
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on_tick = hook;
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}
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/// The timer interrupt handler: advance the monotonic tick count, then run the
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/// tick hook (which may switch tasks). The interrupt is already acknowledged by
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/// the dispatcher before we get here, so a task switch here doesn't stall it.
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pub fn timerTick() void {
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tick_count +%= 1;
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if (on_tick) |hook| hook();
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}
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/// Number of timer ticks so far. Volatile load: the count is bumped
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/// asynchronously by the interrupt handler, so callers must re-read memory.
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pub fn ticks() u64 {
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return @as(*const volatile u64, &tick_count).*;
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}
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@@ -0,0 +1,192 @@
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//! x86_64 CPU operations. This is the "arch" module: the generic kernel imports
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//! it as `@import("arch")` and never names x86_64 directly, so a second
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//! architecture is added by pointing that module at a different directory in
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//! build.zig — no change to the generic code. Keep everything CPU-specific here
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//! (halt, the descriptor tables, later paging), and nothing generic.
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const danos = @import("danos");
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const gdt = @import("gdt.zig");
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const tss = @import("tss.zig");
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const idt = @import("idt.zig");
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const paging = @import("paging.zig");
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const serial = @import("serial.zig");
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const apic = @import("apic.zig");
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/// The saved register/trap frame passed to a fault handler.
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pub const CpuState = idt.CpuState;
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/// Bring up the serial port (the kernel's machine-readable log). No dependencies,
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/// so it can be the very first thing called.
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pub fn serialInit() void {
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serial.init();
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}
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/// Write bytes to the serial port.
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pub fn serialWrite(bytes: []const u8) void {
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serial.write(bytes);
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}
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/// Set up the CPU's descriptor tables: our own GDT, the TSS (with an interrupt
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/// stack for double faults), then the IDT with exception handlers. After this a
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/// CPU fault is reported instead of triple-faulting. Install the fault handler
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/// (setFaultHandler) first so early faults are caught.
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pub fn init() void {
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gdt.init();
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tss.init();
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idt.init();
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}
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/// Build the kernel's own page tables (with real permissions) and switch onto
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/// them. Needs the frame allocator and the boot info (for the memory map and the
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/// kernel's segment layout). Call once the frame allocator is up.
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pub fn enablePaging(allocFrame: *const fn () ?u64, boot_info: *const danos.BootInfo) void {
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paging.init(allocFrame, boot_info);
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}
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/// Map a page into the kernel address space (non-executable). For the heap, etc.
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pub fn mapPage(virt: u64, phys: u64, writable: bool) void {
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paging.map(virt, phys, writable);
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}
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/// Remove a kernel mapping.
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pub fn unmapPage(virt: u64) void {
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paging.unmap(virt);
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}
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/// CR3 holds the physical address of the active top-level page table.
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pub fn readCr3() u64 {
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return asm volatile ("mov %%cr3, %[out]"
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: [out] "=r" (-> u64),
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);
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}
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/// Kernel tick rate: 1000 Hz (1 ms), the scheduler's time quantum.
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pub const timer_hz = 1000;
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/// Enable the Local APIC, calibrate its timer against the PIT, and start it firing
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/// at `timer_hz` — the kernel's real-time heartbeat. Interrupts still have to be
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/// unmasked with enableInterrupts() to be delivered.
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pub fn startTimer() void {
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apic.init();
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apic.calibrate();
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idt.setHandler(apic.timer_vector, apic.timerTick);
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apic.initTimer(timer_hz);
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}
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/// Number of timer ticks since startTimer().
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pub fn ticks() u64 {
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return apic.ticks();
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}
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// Monotonic high-resolution clock (from the TSC), one function per resolution.
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pub fn nanos() u64 {
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return apic.nanos();
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}
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pub fn micros() u64 {
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return apic.micros();
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}
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pub fn millis() u64 {
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return apic.millis();
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}
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/// Measured LAPIC timer / TSC frequencies in Hz (from calibration).
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pub fn lapicHz() u64 {
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return apic.lapicHz();
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}
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pub fn tscHz() u64 {
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return apic.tscHz();
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}
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/// Unmask maskable interrupts (`sti`) so device interrupts get delivered.
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pub fn enableInterrupts() void {
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asm volatile ("sti");
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}
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/// Mask maskable interrupts (`cli`).
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pub fn disableInterrupts() void {
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asm volatile ("cli");
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}
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/// Disable interrupts and return the previous flags, so a nested critical section
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/// can restore the caller's state rather than blindly re-enabling. Pairs with
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/// restoreInterrupts.
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pub fn saveInterrupts() u64 {
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var flags: u64 = undefined;
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asm volatile (
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\\pushfq
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\\pop %[f]
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\\cli
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: [f] "=r" (flags),
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:
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: .{ .memory = true }
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);
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return flags;
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}
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/// Re-enable interrupts only if they were enabled when `flags` was captured.
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pub fn restoreInterrupts(flags: u64) void {
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if (flags & 0x200 != 0) asm volatile ("sti" ::: .{ .memory = true }); // bit 9 = IF
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}
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/// Register a callback the timer interrupt invokes each tick (e.g. the scheduler).
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pub fn setTickHook(hook: *const fn () void) void {
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apic.setTickHook(hook);
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}
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// --- context switching (for the scheduler) -------------------------------
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/// Save the current task's registers/stack and resume `new_rsp`; the old stack
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/// pointer is written to `old_rsp`. Defined in isr.s.
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extern fn switch_context(old_rsp: *usize, new_rsp: usize) callconv(.c) void;
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pub fn switchContext(old_rsp: *usize, new_rsp: usize) void {
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switch_context(old_rsp, new_rsp);
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}
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/// Build the initial stack for a new task so that switching to it lands in
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/// `task_trampoline`, which then calls `entry`. Returns the saved stack pointer.
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/// The layout must match switch_context's push order (callee-saved, then the
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/// return address on top); `entry` is smuggled in via the r15 slot.
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pub fn initTaskStack(stack_top: usize, entry: usize) usize {
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const trampoline = @extern(*const anyopaque, .{ .name = "task_trampoline" });
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var sp = stack_top;
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const push = struct {
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fn f(p: *usize, value: usize) void {
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p.* -= @sizeOf(usize);
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@as(*usize, @ptrFromInt(p.*)).* = value;
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}
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}.f;
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push(&sp, @intFromPtr(trampoline)); // return address for switch_context's `ret`
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push(&sp, 0); // rbx
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push(&sp, 0); // rbp
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push(&sp, 0); // r12
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push(&sp, 0); // r13
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push(&sp, 0); // r14
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push(&sp, entry); // r15 -> task entry, read by task_trampoline
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return sp;
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}
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/// Route CPU exceptions to `handler`, which receives the trap frame and does not
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/// return. Until set, faults just halt the core.
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pub fn setFaultHandler(handler: *const fn (*const CpuState) noreturn) void {
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idt.on_fault = handler;
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}
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/// A human-readable name for a CPU exception vector.
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pub fn vectorName(vector: u64) []const u8 {
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return idt.vectorName(vector);
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}
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/// CR2 holds the faulting linear address after a page fault (#PF, vector 14).
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pub fn readCr2() u64 {
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return asm volatile ("mov %%cr2, %[out]"
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: [out] "=r" (-> u64),
|
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);
|
||||
}
|
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/// Park the core forever. `hlt` drops it into a low-power idle until the next
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/// interrupt; the loop re-halts on every wake so the stop is permanent. See
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/// docs/halting.md for the full reasoning.
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pub fn halt() noreturn {
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while (true) asm volatile ("hlt");
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}
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@@ -0,0 +1,54 @@
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//! Global Descriptor Table. In long mode segmentation is mostly vestigial, but
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//! the CPU still needs valid code/data segment descriptors, and the IDT's gates
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//! reference a code selector — so we install our own flat GDT with known
|
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//! selectors (0x08 kernel code, 0x10 kernel data) rather than trusting whatever
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//! the firmware left in place.
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/// Selectors into the table below (index * 8).
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pub const kernel_code = 0x08;
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pub const kernel_data = 0x10;
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pub const tss_selector = 0x18;
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/// Flat 64-bit descriptors. Base/limit are ignored in long mode; what matters is
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/// the access byte and, for code, the long-mode (L) flag.
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/// code: present, ring 0, executable, readable, L=1 -> 0x00AF9A00_0000FFFF
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/// data: present, ring 0, writable -> 0x00CF9200_0000FFFF
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/// The last two slots hold one 16-byte TSS descriptor, filled in by setTss.
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var table = [_]u64{
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0, // null descriptor (required)
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0x00AF9A000000FFFF, // kernel code (0x08)
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||||
0x00CF92000000FFFF, // kernel data (0x10)
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||||
0, // TSS descriptor low (0x18)
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0, // TSS descriptor high
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||||
};
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||||
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||||
/// Fill the 64-bit TSS system descriptor (two GDT slots) so the task register can
|
||||
/// point at our TSS. Type 0x89 = present, ring 0, available 64-bit TSS.
|
||||
pub fn setTss(base: u64, limit: u64) void {
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||||
table[3] = (limit & 0xFFFF) |
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((base & 0xFFFF) << 16) |
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(((base >> 16) & 0xFF) << 32) |
|
||||
(@as(u64, 0x89) << 40) |
|
||||
(((limit >> 16) & 0xF) << 48) |
|
||||
(((base >> 24) & 0xFF) << 56);
|
||||
table[4] = (base >> 32) & 0xFFFFFFFF;
|
||||
}
|
||||
|
||||
/// The operand `lgdt` wants: table byte-length minus one, then its address.
|
||||
const Descriptor = packed struct {
|
||||
limit: u16,
|
||||
base: u64,
|
||||
};
|
||||
|
||||
/// Loads the GDT and reloads the segment registers (including CS). Defined in
|
||||
/// isr.s — it uses the selectors 0x08 (code) and 0x10 (data) that match `table`.
|
||||
extern fn gdt_flush(descriptor: *const Descriptor) callconv(.c) void;
|
||||
|
||||
/// Install our GDT and switch onto its segments.
|
||||
pub fn init() void {
|
||||
const descriptor = Descriptor{
|
||||
.limit = @sizeOf(@TypeOf(table)) - 1,
|
||||
.base = @intFromPtr(&table),
|
||||
};
|
||||
gdt_flush(&descriptor);
|
||||
}
|
||||
@@ -0,0 +1,155 @@
|
||||
//! Interrupt Descriptor Table, CPU-exception handlers, and device-interrupt
|
||||
//! dispatch. Without this, any fault (a stray pointer, a bad page-table entry)
|
||||
//! triple-faults and silently resets the machine. With it, the CPU vectors into
|
||||
//! our stubs, which capture the register state and hand it to a dispatcher.
|
||||
//!
|
||||
//! Vectors split in two: 0-31 are CPU exceptions (terminal — reported and
|
||||
//! halted); 32+ are device interrupts (a registered handler runs, the APIC is
|
||||
//! acknowledged, and we return to the interrupted code).
|
||||
|
||||
const gdt = @import("gdt.zig");
|
||||
const tss = @import("tss.zig");
|
||||
const apic = @import("apic.zig");
|
||||
|
||||
/// Highest vector we install a gate/stub for (exceptions 0-31 plus the device
|
||||
/// range 32-47, which covers the timer and the spurious vector).
|
||||
const gate_count = 48;
|
||||
|
||||
/// A device-interrupt handler. It doesn't get the trap frame (a timer or keyboard
|
||||
/// handler doesn't need the interrupted registers); add that if one ever does.
|
||||
pub const Handler = *const fn () void;
|
||||
|
||||
var handlers = [_]?Handler{null} ** 256;
|
||||
|
||||
/// Register `handler` for a device-interrupt `vector` (>= 32).
|
||||
pub fn setHandler(vector: usize, handler: Handler) void {
|
||||
handlers[vector] = handler;
|
||||
}
|
||||
|
||||
/// The register + trap frame the ISR stubs build on the stack, laid out so the
|
||||
/// lowest address (where RSP points when we call the handler) is the first field.
|
||||
/// See the push order in `isrCommon` below.
|
||||
pub const CpuState = extern struct {
|
||||
r15: u64,
|
||||
r14: u64,
|
||||
r13: u64,
|
||||
r12: u64,
|
||||
r11: u64,
|
||||
r10: u64,
|
||||
r9: u64,
|
||||
r8: u64,
|
||||
rbp: u64,
|
||||
rdi: u64,
|
||||
rsi: u64,
|
||||
rdx: u64,
|
||||
rcx: u64,
|
||||
rbx: u64,
|
||||
rax: u64,
|
||||
vector: u64, // pushed by the per-vector stub
|
||||
error_code: u64, // real one from the CPU, or 0 pushed by the stub
|
||||
rip: u64, // from here down: pushed by the CPU on entry
|
||||
cs: u64,
|
||||
rflags: u64,
|
||||
rsp: u64,
|
||||
ss: u64,
|
||||
};
|
||||
|
||||
/// Where a fault is reported. The kernel overrides this (see setFaultHandler) with
|
||||
/// something that prints to the console; until then, just stop.
|
||||
pub var on_fault: *const fn (*const CpuState) noreturn = defaultFault;
|
||||
|
||||
fn defaultFault(_: *const CpuState) noreturn {
|
||||
while (true) asm volatile ("hlt");
|
||||
}
|
||||
|
||||
/// Names for the 32 defined exception vectors, for readable output.
|
||||
const names = [_][]const u8{
|
||||
"divide error", "debug",
|
||||
"NMI", "breakpoint",
|
||||
"overflow", "bound range exceeded",
|
||||
"invalid opcode", "device not available",
|
||||
"double fault", "coprocessor segment overrun",
|
||||
"invalid TSS", "segment not present",
|
||||
"stack-segment fault", "general protection fault",
|
||||
"page fault", "reserved (15)",
|
||||
"x87 floating-point", "alignment check",
|
||||
"machine check", "SIMD floating-point",
|
||||
"virtualization", "control protection",
|
||||
"reserved (22)", "reserved (23)",
|
||||
"reserved (24)", "reserved (25)",
|
||||
"reserved (26)", "reserved (27)",
|
||||
"hypervisor injection", "VMM communication",
|
||||
"security exception", "reserved (31)",
|
||||
};
|
||||
|
||||
pub fn vectorName(vector: u64) []const u8 {
|
||||
return if (vector < names.len) names[vector] else "unknown";
|
||||
}
|
||||
|
||||
/// A 64-bit IDT gate descriptor (16 bytes).
|
||||
const Gate = packed struct {
|
||||
offset_low: u16,
|
||||
selector: u16,
|
||||
ist: u8, // interrupt-stack-table index; 0 = use the current stack
|
||||
flags: u8, // present, DPL, gate type
|
||||
offset_mid: u16,
|
||||
offset_high: u32,
|
||||
reserved: u32 = 0,
|
||||
};
|
||||
|
||||
var idt = [_]Gate{std.mem.zeroes(Gate)} ** 256;
|
||||
|
||||
const Descriptor = packed struct {
|
||||
limit: u16,
|
||||
base: u64,
|
||||
};
|
||||
|
||||
/// Loads the IDT (`lidt`). Defined in isr.s.
|
||||
extern fn idt_flush(descriptor: *const Descriptor) callconv(.c) void;
|
||||
|
||||
fn setGate(vector: usize, handler: u64) void {
|
||||
idt[vector] = .{
|
||||
.offset_low = @truncate(handler),
|
||||
.selector = gdt.kernel_code,
|
||||
.ist = 0,
|
||||
.flags = 0x8E, // present, ring 0, 64-bit interrupt gate
|
||||
.offset_mid = @truncate(handler >> 16),
|
||||
.offset_high = @truncate(handler >> 32),
|
||||
};
|
||||
}
|
||||
|
||||
/// Point every installed vector at its stub (isr.s) and load the IDT.
|
||||
pub fn init() void {
|
||||
@setEvalBranchQuota(20000); // comptimePrint across all the gates adds up
|
||||
inline for (0..gate_count) |vector| {
|
||||
const stub = @extern(*const anyopaque, .{ .name = std.fmt.comptimePrint("isr{d}", .{vector}) });
|
||||
setGate(vector, @intFromPtr(stub));
|
||||
}
|
||||
// Run the double-fault handler (vector 8) on IST1: a #DF usually means the
|
||||
// current stack is unusable, so it needs a guaranteed-good one. See tss.zig.
|
||||
idt[8].ist = tss.double_fault_ist;
|
||||
const descriptor = Descriptor{
|
||||
.limit = @sizeOf(@TypeOf(idt)) - 1,
|
||||
.base = @intFromPtr(&idt),
|
||||
};
|
||||
idt_flush(&descriptor);
|
||||
}
|
||||
|
||||
/// Called by isr_common (isr.s) with a pointer to the trap frame. Exported so the
|
||||
/// assembly stubs can `call` it by name. Exceptions are terminal; device
|
||||
/// interrupts run their handler, get acknowledged, and return.
|
||||
export fn interruptDispatch(state: *const CpuState) callconv(.c) void {
|
||||
if (state.vector < 32) {
|
||||
on_fault(state); // CPU exception — never returns
|
||||
} else if (handlers[state.vector]) |handler| {
|
||||
// Acknowledge before running the handler: a handler that switches tasks
|
||||
// (the scheduler) may not return promptly, and the LAPIC mustn't wait on
|
||||
// it to deliver the next interrupt. Fine for edge-triggered sources like
|
||||
// the timer; a level-triggered device would need EOI after handling.
|
||||
apic.eoi();
|
||||
handler();
|
||||
}
|
||||
// else: spurious/unhandled device interrupt — don't acknowledge it
|
||||
}
|
||||
|
||||
const std = @import("std");
|
||||
@@ -0,0 +1,38 @@
|
||||
//! x86 port I/O and model-specific registers — the low-level primitives the
|
||||
//! serial port and the APIC talk to hardware through.
|
||||
|
||||
pub fn outb(port: u16, value: u8) void {
|
||||
asm volatile ("outb %[value], %[port]"
|
||||
:
|
||||
: [value] "{al}" (value),
|
||||
[port] "{dx}" (port),
|
||||
);
|
||||
}
|
||||
|
||||
pub fn inb(port: u16) u8 {
|
||||
return asm volatile ("inb %[port], %[value]"
|
||||
: [value] "={al}" (-> u8),
|
||||
: [port] "{dx}" (port),
|
||||
);
|
||||
}
|
||||
|
||||
/// Read a model-specific register (returns edx:eax combined).
|
||||
pub fn rdmsr(msr: u32) u64 {
|
||||
var low: u32 = undefined;
|
||||
var high: u32 = undefined;
|
||||
asm volatile ("rdmsr"
|
||||
: [low] "={eax}" (low),
|
||||
[high] "={edx}" (high),
|
||||
: [msr] "{ecx}" (msr),
|
||||
);
|
||||
return (@as(u64, high) << 32) | low;
|
||||
}
|
||||
|
||||
pub fn wrmsr(msr: u32, value: u64) void {
|
||||
asm volatile ("wrmsr"
|
||||
:
|
||||
: [msr] "{ecx}" (msr),
|
||||
[low] "{eax}" (@as(u32, @truncate(value))),
|
||||
[high] "{edx}" (@as(u32, @truncate(value >> 32))),
|
||||
);
|
||||
}
|
||||
@@ -0,0 +1,180 @@
|
||||
# x86_64 low-level entry code: the CPU-exception stubs, plus the GDT/IDT load
|
||||
# helpers. Kept in a dedicated assembly file rather than inline asm because these
|
||||
# need real labels and cross-symbol jumps/calls (isr_common, exceptionHandler),
|
||||
# and because `lgdt`/`lidt` memory operands aren't expressible in Zig inline asm.
|
||||
#
|
||||
# Each exception vector normalises the stack to a uniform trap frame — a dummy
|
||||
# error code where the CPU pushes none, then the vector number — and jumps to the
|
||||
# shared tail, which saves the general registers and calls the Zig handler with a
|
||||
# pointer to the frame (matching src/arch/x86_64/idt.zig's CpuState).
|
||||
|
||||
.text
|
||||
|
||||
# gdt_flush(rdi = *GDT descriptor): load the GDT, reload the data segment
|
||||
# registers to the data selector, and reload CS to the code selector. CS can't be
|
||||
# set with mov, so we far-return through the caller's own return address.
|
||||
.global gdt_flush
|
||||
gdt_flush:
|
||||
lgdt (%rdi)
|
||||
mov $0x10, %ax # kernel data selector
|
||||
mov %ax, %ds
|
||||
mov %ax, %es
|
||||
mov %ax, %ss
|
||||
mov %ax, %fs
|
||||
mov %ax, %gs
|
||||
pop %rax # caller's return address
|
||||
push $0x08 # kernel code selector (new CS)
|
||||
push %rax # return address (new RIP)
|
||||
lretq
|
||||
|
||||
# idt_flush(rdi = *IDT descriptor): load the IDT.
|
||||
.global idt_flush
|
||||
idt_flush:
|
||||
lidt (%rdi)
|
||||
ret
|
||||
|
||||
# load_tr(di = TSS selector): load the task register.
|
||||
.global load_tr
|
||||
load_tr:
|
||||
ltr %di
|
||||
ret
|
||||
|
||||
# switch_context(rdi = &old_task.rsp, rsi = new_task.rsp)
|
||||
# Cooperative context switch: save the callee-saved registers on the current
|
||||
# stack, stash the stack pointer in the old task, load the new task's stack
|
||||
# pointer, restore its callee-saved registers, and return into it. Caller-saved
|
||||
# registers are the compiler's responsibility (this looks like a normal call).
|
||||
.global switch_context
|
||||
switch_context:
|
||||
push %rbx
|
||||
push %rbp
|
||||
push %r12
|
||||
push %r13
|
||||
push %r14
|
||||
push %r15
|
||||
mov %rsp, (%rdi) # save old stack pointer into old_task.rsp
|
||||
mov %rsi, %rsp # switch to the new task's stack
|
||||
pop %r15
|
||||
pop %r14
|
||||
pop %r13
|
||||
pop %r12
|
||||
pop %rbp
|
||||
pop %rbx
|
||||
ret # return into the new task's saved instruction pointer
|
||||
|
||||
# task_trampoline: the first thing a freshly-spawned task runs. init_task_stack
|
||||
# leaves its entry function in r15. New tasks start with interrupts enabled.
|
||||
.global task_trampoline
|
||||
task_trampoline:
|
||||
sti
|
||||
call *%r15 # call the task entry (fn() void)
|
||||
1: hlt # if the entry returns, idle (still preemptible)
|
||||
jmp 1b
|
||||
|
||||
# Stub for a vector the CPU does NOT push an error code for: push a dummy 0.
|
||||
.macro STUB_NOERR vec
|
||||
.global isr\vec
|
||||
isr\vec:
|
||||
pushq $0
|
||||
pushq $\vec
|
||||
jmp isr_common
|
||||
.endm
|
||||
|
||||
# Stub for a vector the CPU DOES push an error code for: leave it in place.
|
||||
.macro STUB_ERR vec
|
||||
.global isr\vec
|
||||
isr\vec:
|
||||
pushq $\vec
|
||||
jmp isr_common
|
||||
.endm
|
||||
|
||||
STUB_NOERR 0
|
||||
STUB_NOERR 1
|
||||
STUB_NOERR 2
|
||||
STUB_NOERR 3
|
||||
STUB_NOERR 4
|
||||
STUB_NOERR 5
|
||||
STUB_NOERR 6
|
||||
STUB_NOERR 7
|
||||
STUB_ERR 8
|
||||
STUB_NOERR 9
|
||||
STUB_ERR 10
|
||||
STUB_ERR 11
|
||||
STUB_ERR 12
|
||||
STUB_ERR 13
|
||||
STUB_ERR 14
|
||||
STUB_NOERR 15
|
||||
STUB_NOERR 16
|
||||
STUB_ERR 17
|
||||
STUB_NOERR 18
|
||||
STUB_NOERR 19
|
||||
STUB_NOERR 20
|
||||
STUB_ERR 21
|
||||
STUB_NOERR 22
|
||||
STUB_NOERR 23
|
||||
STUB_NOERR 24
|
||||
STUB_NOERR 25
|
||||
STUB_NOERR 26
|
||||
STUB_NOERR 27
|
||||
STUB_NOERR 28
|
||||
STUB_NOERR 29
|
||||
STUB_NOERR 30
|
||||
STUB_NOERR 31
|
||||
|
||||
# Device-interrupt vectors (timer, spurious, room for more). None push an error
|
||||
# code, so they all use the dummy-zero form.
|
||||
STUB_NOERR 32
|
||||
STUB_NOERR 33
|
||||
STUB_NOERR 34
|
||||
STUB_NOERR 35
|
||||
STUB_NOERR 36
|
||||
STUB_NOERR 37
|
||||
STUB_NOERR 38
|
||||
STUB_NOERR 39
|
||||
STUB_NOERR 40
|
||||
STUB_NOERR 41
|
||||
STUB_NOERR 42
|
||||
STUB_NOERR 43
|
||||
STUB_NOERR 44
|
||||
STUB_NOERR 45
|
||||
STUB_NOERR 46
|
||||
STUB_NOERR 47
|
||||
|
||||
.extern interruptDispatch
|
||||
|
||||
# Shared tail. Register push order here defines the CpuState field order.
|
||||
isr_common:
|
||||
push %rax
|
||||
push %rbx
|
||||
push %rcx
|
||||
push %rdx
|
||||
push %rsi
|
||||
push %rdi
|
||||
push %rbp
|
||||
push %r8
|
||||
push %r9
|
||||
push %r10
|
||||
push %r11
|
||||
push %r12
|
||||
push %r13
|
||||
push %r14
|
||||
push %r15
|
||||
mov %rsp, %rdi # first argument: pointer to the trap frame
|
||||
call interruptDispatch
|
||||
pop %r15
|
||||
pop %r14
|
||||
pop %r13
|
||||
pop %r12
|
||||
pop %r11
|
||||
pop %r10
|
||||
pop %r9
|
||||
pop %r8
|
||||
pop %rbp
|
||||
pop %rdi
|
||||
pop %rsi
|
||||
pop %rdx
|
||||
pop %rcx
|
||||
pop %rbx
|
||||
pop %rax
|
||||
add $16, %rsp # drop the vector and error code
|
||||
iretq
|
||||
@@ -0,0 +1,47 @@
|
||||
/* Kernel link layout.
|
||||
*
|
||||
* The kernel is linked at a fixed low physical address (set by `image_base` in
|
||||
* build.zig). UEFI runs with memory identity-mapped, so the bootloader can load
|
||||
* each PT_LOAD segment to the physical address matching its virtual address and
|
||||
* jump straight to _start — no page tables to build yet. (Moving to a
|
||||
* higher-half virtual base is a later step, once the bootloader sets up paging.)
|
||||
*/
|
||||
|
||||
ENTRY(_start)
|
||||
|
||||
/* One loadable segment per permission set, so the loader can map .text as R+X,
|
||||
* .rodata as R, and .data/.bss as R+W. FLAGS bits: 1=X, 2=W, 4=R. */
|
||||
PHDRS {
|
||||
text PT_LOAD FLAGS(5); /* R + X */
|
||||
rodata PT_LOAD FLAGS(4); /* R */
|
||||
data PT_LOAD FLAGS(6); /* R + W */
|
||||
}
|
||||
|
||||
SECTIONS {
|
||||
.text ALIGN(4K) : {
|
||||
*(.text .text.*)
|
||||
} :text
|
||||
|
||||
.rodata ALIGN(4K) : {
|
||||
*(.rodata .rodata.*)
|
||||
} :rodata
|
||||
|
||||
.data ALIGN(4K) : {
|
||||
*(.data .data.*)
|
||||
} :data
|
||||
|
||||
/* .bss occupies memory but not file space. The loader zeroes it via the
|
||||
* gap between each PT_LOAD segment's file size and memory size, so no
|
||||
* boundary symbols are needed here. (Zig's self-hosted linker also does not
|
||||
* yet honour linker-script symbol assignments.) */
|
||||
.bss ALIGN(4K) : {
|
||||
*(.bss .bss.*)
|
||||
*(COMMON)
|
||||
} :data
|
||||
|
||||
/DISCARD/ : {
|
||||
*(.comment)
|
||||
*(.note .note.*)
|
||||
*(.eh_frame .eh_frame_hdr)
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,153 @@
|
||||
//! The kernel's page tables and virtual memory manager.
|
||||
//!
|
||||
//! Builds our own 4-level page tables and switches CR3 onto them, replacing the
|
||||
//! firmware's. Unlike the earlier bootstrap this maps with real permissions:
|
||||
//! RAM is identity-mapped read-write + no-execute, the kernel's own segments get
|
||||
//! their ELF permissions (code R+X, rodata R, data R+W+NX), and page 0 is left
|
||||
//! unmapped as a null guard. It also exposes map/unmap for on-demand mapping,
|
||||
//! which the kernel heap will build on.
|
||||
//!
|
||||
//! Everything is 4 KiB pages — precise and simple; the extra table memory is
|
||||
//! negligible against available RAM.
|
||||
|
||||
const danos = @import("danos");
|
||||
const io = @import("io.zig");
|
||||
|
||||
const page_size = danos.page_size;
|
||||
|
||||
// Page-table entry bits.
|
||||
const present: u64 = 1 << 0;
|
||||
const writable: u64 = 1 << 1;
|
||||
const no_execute: u64 = 1 << 63;
|
||||
const addr_mask: u64 = 0x000F_FFFF_FFFF_F000;
|
||||
|
||||
// ELF segment flags (p_flags).
|
||||
const pf_x: u32 = 1;
|
||||
const pf_w: u32 = 2;
|
||||
|
||||
// State kept after init so map()/unmap() can serve later callers (e.g. the heap).
|
||||
var kernel_pml4: u64 = 0;
|
||||
var alloc_frame: *const fn () ?u64 = undefined;
|
||||
|
||||
fn tableAt(phys: u64) *[512]u64 {
|
||||
return @ptrFromInt(phys);
|
||||
}
|
||||
|
||||
fn allocTable() u64 {
|
||||
const frame = alloc_frame() orelse @panic("paging: out of memory building page tables");
|
||||
@memset(tableAt(frame)[0..], 0);
|
||||
return frame;
|
||||
}
|
||||
|
||||
/// Return the table an entry points at, creating it if empty. Intermediate
|
||||
/// entries are writable and executable so the leaf's bits govern (a page is
|
||||
/// writable only if every level is; non-executable if any level is).
|
||||
fn descend(entry: *u64) u64 {
|
||||
if (entry.* & present != 0) return entry.* & addr_mask;
|
||||
const frame = allocTable();
|
||||
entry.* = frame | present | writable;
|
||||
return frame;
|
||||
}
|
||||
|
||||
/// Map one 4 KiB page `virt` -> `phys` with `flags` (present is added).
|
||||
fn mapPage(pml4: u64, virt: u64, phys: u64, flags: u64) void {
|
||||
const pml4e = &tableAt(pml4)[(virt >> 39) & 0x1FF];
|
||||
const pdpt = descend(pml4e);
|
||||
const pdpte = &tableAt(pdpt)[(virt >> 30) & 0x1FF];
|
||||
const pd = descend(pdpte);
|
||||
const pde = &tableAt(pd)[(virt >> 21) & 0x1FF];
|
||||
const pt = descend(pde);
|
||||
tableAt(pt)[(virt >> 12) & 0x1FF] = (phys & addr_mask) | flags | present;
|
||||
}
|
||||
|
||||
/// Identity-map [base, base+len) with `flags`, rounded out to whole pages.
|
||||
fn mapRangeIdentity(pml4: u64, base: u64, len: u64, flags: u64) void {
|
||||
var addr = base & ~@as(u64, page_size - 1);
|
||||
const end = base + len;
|
||||
while (addr < end) : (addr += page_size) {
|
||||
if (addr == 0) continue; // leave page 0 unmapped: the null guard
|
||||
mapPage(pml4, addr, addr, flags);
|
||||
}
|
||||
}
|
||||
|
||||
fn regions(mm: danos.MemoryMap) []const danos.MemoryRegion {
|
||||
return @as([*]const danos.MemoryRegion, @ptrFromInt(mm.regions))[0..mm.len];
|
||||
}
|
||||
|
||||
/// Enable the NX bit in the page-table format (EFER.NXE). Must happen before we
|
||||
/// load a CR3 whose entries set the NX bit, or those bits are reserved and fault.
|
||||
fn enableNx() void {
|
||||
const efer_msr = 0xC0000080;
|
||||
io.wrmsr(efer_msr, io.rdmsr(efer_msr) | (1 << 11));
|
||||
}
|
||||
|
||||
/// Build the address space and switch onto it.
|
||||
pub fn init(allocFrame: *const fn () ?u64, boot_info: *const danos.BootInfo) void {
|
||||
alloc_frame = allocFrame;
|
||||
enableNx();
|
||||
const pml4 = allocTable();
|
||||
|
||||
// 1. All RAM identity-mapped RW + NX. Non-RAM (MMIO) is skipped and stays
|
||||
// unmapped unless mapped explicitly below.
|
||||
for (regions(boot_info.memory_map)) |r| {
|
||||
if (r.kind == .mmio) continue;
|
||||
mapRangeIdentity(pml4, r.base, r.pages * page_size, present | writable | no_execute);
|
||||
}
|
||||
|
||||
// 2. The framebuffer and the Local APIC (device memory we need), RW + NX.
|
||||
const fb = boot_info.framebuffer;
|
||||
mapRangeIdentity(pml4, fb.base, @as(u64, fb.height) * fb.pitch, present | writable | no_execute);
|
||||
mapPage(pml4, 0xFEE00000, 0xFEE00000, present | writable | no_execute);
|
||||
|
||||
// 3. Overlay the kernel's own segments with their real ELF permissions,
|
||||
// replacing the blanket RW+NX from step 1: code becomes R+X, rodata R,
|
||||
// data R+W+NX. This is the W^X guarantee.
|
||||
for (boot_info.kernel_segments[0..boot_info.kernel_segment_count]) |seg| {
|
||||
var flags: u64 = present;
|
||||
if (seg.flags & pf_w != 0) flags |= writable;
|
||||
if (seg.flags & pf_x == 0) flags |= no_execute;
|
||||
var addr = seg.virt;
|
||||
const end = seg.virt + seg.pages * page_size;
|
||||
while (addr < end) : (addr += page_size) mapPage(pml4, addr, addr, flags);
|
||||
}
|
||||
|
||||
kernel_pml4 = pml4;
|
||||
asm volatile ("mov %[pml4], %%cr3"
|
||||
:
|
||||
: [pml4] "r" (pml4),
|
||||
: .{ .memory = true }
|
||||
);
|
||||
}
|
||||
|
||||
/// Map a page into the kernel address space on demand (for the heap, etc.).
|
||||
/// `writable_page` controls W; pages are always mapped non-executable.
|
||||
pub fn map(virt: u64, phys: u64, writable_page: bool) void {
|
||||
var flags: u64 = present | no_execute;
|
||||
if (writable_page) flags |= writable;
|
||||
mapPage(kernel_pml4, virt, phys, flags);
|
||||
invalidate(virt);
|
||||
}
|
||||
|
||||
/// Remove a mapping and flush it from the TLB.
|
||||
pub fn unmap(virt: u64) void {
|
||||
const pml4e = tableAt(kernel_pml4)[(virt >> 39) & 0x1FF];
|
||||
if (pml4e & present == 0) return;
|
||||
const pdpte = tableAt(pml4e & addr_mask)[(virt >> 30) & 0x1FF];
|
||||
if (pdpte & present == 0) return;
|
||||
const pde = tableAt(pdpte & addr_mask)[(virt >> 21) & 0x1FF];
|
||||
if (pde & present == 0) return;
|
||||
tableAt(pde & addr_mask)[(virt >> 12) & 0x1FF] = 0;
|
||||
invalidate(virt);
|
||||
}
|
||||
|
||||
fn invalidate(virt: u64) void {
|
||||
// invlpg needs its operand via a register-indirect memory reference that Zig
|
||||
// inline asm won't form directly, so stage the address in a register first.
|
||||
asm volatile (
|
||||
\\mov %[v], %%rax
|
||||
\\invlpg (%%rax)
|
||||
:
|
||||
: [v] "r" (virt),
|
||||
: .{ .rax = true, .memory = true }
|
||||
);
|
||||
}
|
||||
@@ -0,0 +1,46 @@
|
||||
//! COM1 serial port (16550 UART) — the kernel's machine-readable output channel.
|
||||
//! Unlike the framebuffer console, serial text can be captured to a file by QEMU
|
||||
//! (`-serial file:...`), which is what the test harness asserts on. Each
|
||||
//! architecture has its own UART; this is the x86 one, driven by port I/O.
|
||||
|
||||
const port = 0x3F8; // COM1 base
|
||||
|
||||
fn outb(p: u16, value: u8) void {
|
||||
asm volatile ("outb %[value], %[p]"
|
||||
:
|
||||
: [value] "{al}" (value),
|
||||
[p] "{dx}" (p),
|
||||
);
|
||||
}
|
||||
|
||||
fn inb(p: u16) u8 {
|
||||
return asm volatile ("inb %[p], %[value]"
|
||||
: [value] "={al}" (-> u8),
|
||||
: [p] "{dx}" (p),
|
||||
);
|
||||
}
|
||||
|
||||
/// Configure the UART: 38400 baud, 8N1, FIFO on. Safe to call before anything
|
||||
/// else; it has no dependencies.
|
||||
pub fn init() void {
|
||||
outb(port + 1, 0x00); // disable interrupts
|
||||
outb(port + 3, 0x80); // enable DLAB (set baud divisor)
|
||||
outb(port + 0, 0x03); // divisor low: 38400 baud
|
||||
outb(port + 1, 0x00); // divisor high
|
||||
outb(port + 3, 0x03); // 8 bits, no parity, one stop bit; DLAB off
|
||||
outb(port + 2, 0xC7); // enable + clear FIFO, 14-byte threshold
|
||||
outb(port + 4, 0x0B); // RTS/DSR set
|
||||
}
|
||||
|
||||
fn writeByte(c: u8) void {
|
||||
while (inb(port + 5) & 0x20 == 0) {} // wait until the transmit holding register is empty
|
||||
outb(port, c);
|
||||
}
|
||||
|
||||
/// Write bytes, translating LF to CRLF so terminals and logs line up.
|
||||
pub fn write(bytes: []const u8) void {
|
||||
for (bytes) |c| {
|
||||
if (c == '\n') writeByte('\r');
|
||||
writeByte(c);
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,48 @@
|
||||
//! Task State Segment and its interrupt stack. In long mode the TSS's main job
|
||||
//! is the Interrupt Stack Table: an IDT gate can name an IST entry, and the CPU
|
||||
//! switches to that stack when the exception fires — no matter how broken the
|
||||
//! interrupted stack was. We use IST1 for the double-fault handler, so a fault
|
||||
//! that happens *because* the current stack is unusable still lands on solid
|
||||
//! ground instead of triple-faulting.
|
||||
|
||||
const gdt = @import("gdt.zig");
|
||||
|
||||
/// x86_64 TSS. `packed` because several 64-bit fields sit at 4-byte-unaligned
|
||||
/// offsets (rsp0 at byte 4), which a normal struct would pad away.
|
||||
const Tss = packed struct {
|
||||
reserved0: u32 = 0,
|
||||
rsp0: u64 = 0,
|
||||
rsp1: u64 = 0,
|
||||
rsp2: u64 = 0,
|
||||
reserved1: u64 = 0,
|
||||
ist1: u64 = 0,
|
||||
ist2: u64 = 0,
|
||||
ist3: u64 = 0,
|
||||
ist4: u64 = 0,
|
||||
ist5: u64 = 0,
|
||||
ist6: u64 = 0,
|
||||
ist7: u64 = 0,
|
||||
reserved2: u64 = 0,
|
||||
reserved3: u16 = 0,
|
||||
iomap_base: u16 = 0,
|
||||
};
|
||||
|
||||
/// The IST slot (1-based, as the IDT gate encodes it) used for critical faults.
|
||||
pub const double_fault_ist = 1;
|
||||
|
||||
var tss: Tss align(16) = .{};
|
||||
|
||||
/// Dedicated stack for IST1. Static so it needs no allocator and is always valid.
|
||||
var ist1_stack: [16 * 1024]u8 align(16) = undefined;
|
||||
|
||||
/// Loads the task register with the TSS selector. Defined in isr.s.
|
||||
extern fn load_tr(selector: u16) callconv(.c) void;
|
||||
|
||||
/// Point IST1 at its stack, publish the TSS through the GDT, and load it into the
|
||||
/// task register. Requires the GDT to already be loaded (gdt.init first).
|
||||
pub fn init() void {
|
||||
tss.ist1 = @intFromPtr(&ist1_stack) + ist1_stack.len; // stacks grow down
|
||||
tss.iomap_base = @sizeOf(Tss); // == limit: no I/O permission bitmap
|
||||
gdt.setTss(@intFromPtr(&tss), @sizeOf(Tss) - 1);
|
||||
load_tr(gdt.tss_selector);
|
||||
}
|
||||
Reference in New Issue
Block a user