moving kernel code to kernel/

2026-07-05 10:19:11 +01:00
parent 7c3cffb337
commit 6f6ccc8bc9
37 changed files with 63 additions and 61 deletions
@@ -0,0 +1,202 @@
+//! Local APIC and its timer — the source of device interrupts.
+//!
+//! Modern x86 routes interrupts through the per-CPU Local APIC (the legacy 8259
+//! PIC is remapped out of the way and masked). The LAPIC also has a built-in
+//! timer, which is the simplest device interrupt to bring up: it needs no
+//! external routing, just a vector and a count. We use it as danos's heartbeat.
+//!
+//! The LAPIC is memory-mapped (default physical 0xFEE00000, inside our identity
+//! map). Every interrupt must be acknowledged with an end-of-interrupt write, or
+//! the LAPIC won't deliver the next one.
+
+const io = @import("io.zig");
+
+/// IDT vector the timer fires on (in the device range, >= 32).
+pub const timer_vector = 32;
+/// Spurious-interrupt vector. Low nibble 0xF by convention; also in our gate
+/// range so a stray spurious interrupt lands on a valid (no-op) handler.
+const spurious_vector = 47;
+
+// LAPIC register offsets.
+const reg_spurious = 0x0F0;
+const reg_eoi = 0x0B0;
+const reg_lvt_timer = 0x320;
+const reg_timer_initial = 0x380;
+const reg_timer_current = 0x390;
+const reg_timer_divide = 0x3E0;
+
+const lvt_masked = 1 << 16;
+const lvt_periodic = 1 << 17;
+const timer_divide_16 = 0x3;
+
+const ia32_apic_base_msr = 0x1B;
+
+/// LAPIC MMIO base. A runtime var (not a constant) both because we read it from
+/// the MSR and so register writes compile to normal stores rather than a
+/// `mov moffs`, which the self-hosted backend can't encode.
+var base: usize = 0xFEE00000;
+
+var tick_count: u64 = 0;
+
+/// LAPIC timer counts per millisecond, measured against the PIT (see calibrate).
+/// At divide-by-16, this is the effective counting rate.
+var ticks_per_ms: u32 = 0;
+/// The periodic-interrupt frequency the timer is armed at, once initTimer runs.
+var timer_hz: u32 = 0;
+
+/// TSC (Time Stamp Counter) calibration: cycles per second, and the count at boot.
+/// The TSC is a per-core cycle counter, giving a ~nanosecond high-resolution
+/// monotonic clock — far finer than the millisecond timer tick.
+var tsc_hz: u64 = 0;
+var tsc_base: u64 = 0;
+
+/// Read the 64-bit Time Stamp Counter.
+fn rdtsc() u64 {
+    var low: u32 = undefined;
+    var high: u32 = undefined;
+    asm volatile ("rdtsc"
+        : [low] "={eax}" (low),
+          [high] "={edx}" (high),
+    );
+    return (@as(u64, high) << 32) | low;
+}
+
+fn read(reg: u32) u32 {
+    return @as(*volatile u32, @ptrFromInt(base + reg)).*;
+}
+fn write(reg: u32, value: u32) void {
+    @as(*volatile u32, @ptrFromInt(base + reg)).* = value;
+}
+
+/// Move the legacy 8259 PIC's vectors to 0x20-0x2F (clear of the CPU exception
+/// vectors) and mask every line, so it can't deliver interrupts behind the APIC.
+fn remapAndMaskPic() void {
+    io.outb(0x20, 0x11); // start init (cascade mode)
+    io.outb(0xA0, 0x11);
+    io.outb(0x21, 0x20); // master offset 0x20
+    io.outb(0xA1, 0x28); // slave offset 0x28
+    io.outb(0x21, 0x04); // tell master about slave on IRQ2
+    io.outb(0xA1, 0x02);
+    io.outb(0x21, 0x01); // 8086 mode
+    io.outb(0xA1, 0x01);
+    io.outb(0x21, 0xFF); // mask all
+    io.outb(0xA1, 0xFF);
+}
+
+/// Enable the Local APIC: mask the PIC, set the global-enable MSR bit, and
+/// software-enable the APIC via its spurious-vector register.
+pub fn init() void {
+    remapAndMaskPic();
+
+    const msr = io.rdmsr(ia32_apic_base_msr);
+    base = @intCast(msr & 0xFFFFF000); // physical base is bits 12+
+    io.wrmsr(ia32_apic_base_msr, msr | (1 << 11)); // global enable
+
+    write(reg_spurious, 0x100 | spurious_vector); // bit 8 = software enable
+}
+
+/// Measure the LAPIC timer's and the TSC's rates against the PIT (channel 2, which
+/// can be polled without interrupts). We run the LAPIC timer one-shot from its max
+/// count and snapshot the TSC while the PIT counts out a known 10 ms, then see how
+/// far each got. This gives real time, which the RTOS timing guarantees depend on.
+pub fn calibrate() void {
+    const pit_hz = 1_193_182;
+    const calib_ms = 10;
+    const pit_count: u16 = @intCast(pit_hz / 1000 * calib_ms);
+
+    // LAPIC timer: divide 16, masked (no interrupt — we just want the count),
+    // counting down from the maximum.
+    write(reg_timer_divide, timer_divide_16);
+    write(reg_lvt_timer, lvt_masked);
+    write(reg_timer_initial, 0xFFFFFFFF);
+
+    // PIT channel 2, mode 0 (interrupt on terminal count): load the count with the
+    // gate low, then raise the gate to start it counting.
+    io.outb(0x61, io.inb(0x61) & 0xFC); // speaker off, gate low
+    io.outb(0x43, 0xB0); // channel 2, lo/hi byte, mode 0
+    io.outb(0x42, @truncate(pit_count));
+    io.outb(0x42, @truncate(pit_count >> 8));
+
+    const tsc_start = rdtsc();
+    io.outb(0x61, (io.inb(0x61) & 0xFC) | 0x01); // gate high -> start
+    while (io.inb(0x61) & 0x20 == 0) {} // poll channel-2 output until terminal count
+    const tsc_end = rdtsc();
+
+    const elapsed = 0xFFFFFFFF - read(reg_timer_current);
+    write(reg_timer_initial, 0); // stop the timer
+
+    ticks_per_ms = elapsed / calib_ms;
+    tsc_hz = (tsc_end -% tsc_start) * (1000 / calib_ms); // cycles/10ms -> cycles/s
+    tsc_base = rdtsc(); // the clock's zero point (boot)
+}
+
+/// Arm the LAPIC timer to fire on `timer_vector` at `hz` (periodic). Requires
+/// calibrate() to have run.
+pub fn initTimer(hz: u32) void {
+    timer_hz = hz;
+    const count = @as(u64, ticks_per_ms) * 1000 / hz; // counts per (1/hz) second
+    write(reg_timer_divide, timer_divide_16);
+    write(reg_lvt_timer, timer_vector | lvt_periodic);
+    write(reg_timer_initial, @intCast(count));
+}
+
+/// Configured periodic-interrupt frequency (Hz).
+pub fn frequencyHz() u32 {
+    return timer_hz;
+}
+
+/// Measured LAPIC timer frequency (Hz), for reporting/sanity checks.
+pub fn lapicHz() u64 {
+    return @as(u64, ticks_per_ms) * 1000;
+}
+
+/// Measured TSC frequency (Hz).
+pub fn tscHz() u64 {
+    return tsc_hz;
+}
+
+// Monotonic high-resolution clock, from the TSC. A function per resolution, each
+// scaling the cycle delta directly at its unit (the 128-bit intermediate avoids
+// overflow across a long uptime). nanos() resolves to a few ns; millis() is what
+// the scheduler uses for sleep deadlines.
+
+pub fn nanos() u64 {
+    if (tsc_hz == 0) return 0;
+    return @intCast(@as(u128, rdtsc() -% tsc_base) * 1_000_000_000 / tsc_hz);
+}
+
+pub fn micros() u64 {
+    if (tsc_hz == 0) return 0;
+    return @intCast(@as(u128, rdtsc() -% tsc_base) * 1_000_000 / tsc_hz);
+}
+
+pub fn millis() u64 {
+    if (tsc_hz == 0) return 0;
+    return @intCast(@as(u128, rdtsc() -% tsc_base) * 1_000 / tsc_hz);
+}
+
+/// Acknowledge the current interrupt so the LAPIC will deliver the next one.
+pub fn eoi() void {
+    write(reg_eoi, 0);
+}
+
+/// Optional callback run each tick (the scheduler registers it for preemption).
+var on_tick: ?*const fn () void = null;
+
+pub fn setTickHook(hook: *const fn () void) void {
+    on_tick = hook;
+}
+
+/// The timer interrupt handler: advance the monotonic tick count, then run the
+/// tick hook (which may switch tasks). The interrupt is already acknowledged by
+/// the dispatcher before we get here, so a task switch here doesn't stall it.
+pub fn timerTick() void {
+    tick_count +%= 1;
+    if (on_tick) |hook| hook();
+}
+
+/// Number of timer ticks so far. Volatile load: the count is bumped
+/// asynchronously by the interrupt handler, so callers must re-read memory.
+pub fn ticks() u64 {
+    return @as(*const volatile u64, &tick_count).*;
+}