moving kernel code to kernel/
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# x86_64 low-level entry code: the CPU-exception stubs, plus the GDT/IDT load
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# helpers. Kept in a dedicated assembly file rather than inline asm because these
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# need real labels and cross-symbol jumps/calls (isr_common, exceptionHandler),
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# and because `lgdt`/`lidt` memory operands aren't expressible in Zig inline asm.
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#
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# Each exception vector normalises the stack to a uniform trap frame — a dummy
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# error code where the CPU pushes none, then the vector number — and jumps to the
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# shared tail, which saves the general registers and calls the Zig handler with a
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# pointer to the frame (matching src/arch/x86_64/idt.zig's CpuState).
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.text
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# gdt_flush(rdi = *GDT descriptor): load the GDT, reload the data segment
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# registers to the data selector, and reload CS to the code selector. CS can't be
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# set with mov, so we far-return through the caller's own return address.
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.global gdt_flush
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gdt_flush:
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lgdt (%rdi)
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mov $0x10, %ax # kernel data selector
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mov %ax, %ds
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mov %ax, %es
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mov %ax, %ss
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mov %ax, %fs
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mov %ax, %gs
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pop %rax # caller's return address
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push $0x08 # kernel code selector (new CS)
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push %rax # return address (new RIP)
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lretq
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# idt_flush(rdi = *IDT descriptor): load the IDT.
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.global idt_flush
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idt_flush:
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lidt (%rdi)
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ret
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# load_tr(di = TSS selector): load the task register.
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.global load_tr
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load_tr:
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ltr %di
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ret
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# switch_context(rdi = &old_task.rsp, rsi = new_task.rsp)
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# Cooperative context switch: save the callee-saved registers on the current
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# stack, stash the stack pointer in the old task, load the new task's stack
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# pointer, restore its callee-saved registers, and return into it. Caller-saved
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# registers are the compiler's responsibility (this looks like a normal call).
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.global switch_context
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switch_context:
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push %rbx
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push %rbp
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push %r12
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push %r13
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push %r14
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push %r15
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mov %rsp, (%rdi) # save old stack pointer into old_task.rsp
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mov %rsi, %rsp # switch to the new task's stack
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pop %r15
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pop %r14
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pop %r13
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pop %r12
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pop %rbp
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pop %rbx
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ret # return into the new task's saved instruction pointer
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# task_trampoline: the first thing a freshly-spawned task runs. init_task_stack
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# leaves its entry function in r15. New tasks start with interrupts enabled.
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.global task_trampoline
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task_trampoline:
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sti
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call *%r15 # call the task entry (fn() void)
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1: hlt # if the entry returns, idle (still preemptible)
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jmp 1b
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# Stub for a vector the CPU does NOT push an error code for: push a dummy 0.
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.macro STUB_NOERR vec
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.global isr\vec
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isr\vec:
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pushq $0
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pushq $\vec
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jmp isr_common
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.endm
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# Stub for a vector the CPU DOES push an error code for: leave it in place.
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.macro STUB_ERR vec
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.global isr\vec
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isr\vec:
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pushq $\vec
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jmp isr_common
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.endm
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STUB_NOERR 0
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STUB_NOERR 1
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STUB_NOERR 2
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STUB_NOERR 3
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STUB_NOERR 4
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STUB_NOERR 5
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STUB_NOERR 6
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STUB_NOERR 7
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STUB_ERR 8
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STUB_NOERR 9
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STUB_ERR 10
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STUB_ERR 11
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STUB_ERR 12
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STUB_ERR 13
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STUB_ERR 14
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STUB_NOERR 15
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STUB_NOERR 16
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STUB_ERR 17
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STUB_NOERR 18
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STUB_NOERR 19
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STUB_NOERR 20
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STUB_ERR 21
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STUB_NOERR 22
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STUB_NOERR 23
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STUB_NOERR 24
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STUB_NOERR 25
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STUB_NOERR 26
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STUB_NOERR 27
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STUB_NOERR 28
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STUB_NOERR 29
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STUB_NOERR 30
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STUB_NOERR 31
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# Device-interrupt vectors (timer, spurious, room for more). None push an error
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# code, so they all use the dummy-zero form.
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STUB_NOERR 32
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STUB_NOERR 33
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STUB_NOERR 34
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STUB_NOERR 35
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STUB_NOERR 36
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STUB_NOERR 37
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STUB_NOERR 38
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STUB_NOERR 39
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STUB_NOERR 40
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STUB_NOERR 41
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STUB_NOERR 42
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STUB_NOERR 43
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STUB_NOERR 44
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STUB_NOERR 45
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STUB_NOERR 46
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STUB_NOERR 47
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.extern interruptDispatch
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# Shared tail. Register push order here defines the CpuState field order.
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isr_common:
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push %rax
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push %rbx
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push %rcx
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push %rdx
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push %rsi
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push %rdi
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push %rbp
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push %r8
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push %r9
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push %r10
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push %r11
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push %r12
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push %r13
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push %r14
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push %r15
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mov %rsp, %rdi # first argument: pointer to the trap frame
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call interruptDispatch
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pop %r15
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pop %r14
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pop %r13
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pop %r12
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pop %r11
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pop %r10
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pop %r9
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pop %r8
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pop %rbp
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pop %rdi
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pop %rsi
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pop %rdx
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pop %rcx
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pop %rbx
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pop %rax
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add $16, %rsp # drop the vector and error code
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iretq
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