moving kernel code to kernel/

src/kernel/arch/x86_64/tss.zig

@@ -0,0 +1,48 @@
+//! Task State Segment and its interrupt stack. In long mode the TSS's main job
+//! is the Interrupt Stack Table: an IDT gate can name an IST entry, and the CPU
+//! switches to that stack when the exception fires — no matter how broken the
+//! interrupted stack was. We use IST1 for the double-fault handler, so a fault
+//! that happens *because* the current stack is unusable still lands on solid
+//! ground instead of triple-faulting.
+
+const gdt = @import("gdt.zig");
+
+/// x86_64 TSS. `packed` because several 64-bit fields sit at 4-byte-unaligned
+/// offsets (rsp0 at byte 4), which a normal struct would pad away.
+const Tss = packed struct {
+    reserved0: u32 = 0,
+    rsp0: u64 = 0,
+    rsp1: u64 = 0,
+    rsp2: u64 = 0,
+    reserved1: u64 = 0,
+    ist1: u64 = 0,
+    ist2: u64 = 0,
+    ist3: u64 = 0,
+    ist4: u64 = 0,
+    ist5: u64 = 0,
+    ist6: u64 = 0,
+    ist7: u64 = 0,
+    reserved2: u64 = 0,
+    reserved3: u16 = 0,
+    iomap_base: u16 = 0,
+};
+
+/// The IST slot (1-based, as the IDT gate encodes it) used for critical faults.
+pub const double_fault_ist = 1;
+
+var tss: Tss align(16) = .{};
+
+/// Dedicated stack for IST1. Static so it needs no allocator and is always valid.
+var ist1_stack: [16 * 1024]u8 align(16) = undefined;
+
+/// Loads the task register with the TSS selector. Defined in isr.s.
+extern fn load_tr(selector: u16) callconv(.c) void;
+
+/// Point IST1 at its stack, publish the TSS through the GDT, and load it into the
+/// task register. Requires the GDT to already be loaded (gdt.init first).
+pub fn init() void {
+    tss.ist1 = @intFromPtr(&ist1_stack) + ist1_stack.len; // stacks grow down
+    tss.iomap_base = @sizeOf(Tss); // == limit: no I/O permission bitmap
+    gdt.setTss(@intFromPtr(&tss), @sizeOf(Tss) - 1);
+    load_tr(gdt.tss_selector);
+}