gather kernel tunables into config.zig

max_cpus, max_tasks, kernel/IST stack sizes, and timer_hz move from scattered constants into one config module. root.zig goes back to being just the boot contract. Values unchanged; any can become a -D build option later.
This commit is contained in:
Daniel Samson
2026-07-08 16:26:36 +01:00
parent 1b47de5058
commit 7501bd1703
9 changed files with 56 additions and 21 deletions
+3 -2
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@@ -5,6 +5,7 @@
//! (halt, the descriptor tables, later paging), and nothing generic.
const danos = @import("danos");
const config = @import("config");
const gdt = @import("gdt.zig");
const tss = @import("tss.zig");
const idt = @import("idt.zig");
@@ -148,8 +149,8 @@ pub fn pageExecutable(virt: u64) bool {
return paging.isExecutable(virt);
}
/// Kernel tick rate: 1000 Hz (1 ms), the scheduler's time quantum.
pub const timer_hz = 1000;
/// Kernel tick rate (the scheduler's time quantum), from config.
pub const timer_hz = config.timer_hz;
/// The ACPI PM timer, as a calibration reference (re-exported for the config).
pub const PmTimer = apic.PmTimer;
+2 -2
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@@ -9,14 +9,14 @@
//! tss.zig). Two cores can't share one TSS descriptor slot, so each core gets its
//! own copy of the table with its own TSS descriptor. Slot 0 is the BSP.
const danos = @import("danos");
const config = @import("config");
/// Selectors into the table (index * 8). Same on every core's GDT.
pub const kernel_code = 0x08;
pub const kernel_data = 0x10;
pub const tss_selector = 0x18;
const max_cpus = danos.max_cpus;
const max_cpus = config.max_cpus;
const entries = 5; // null, code, data, TSS-low, TSS-high
/// The shared descriptors (slots 0-2); slots 3-4 hold this core's TSS descriptor,
+3 -3
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@@ -9,7 +9,7 @@
//! once can't share one fault stack. So the TSS and its IST stack are per-core,
//! indexed by CPU number; slot 0 is the BSP.
const danos = @import("danos");
const config = @import("config");
const gdt = @import("gdt.zig");
/// x86_64 TSS. `packed` because several 64-bit fields sit at 4-byte-unaligned
@@ -35,8 +35,8 @@ const Tss = packed struct {
/// The IST slot (1-based, as the IDT gate encodes it) used for critical faults.
pub const double_fault_ist = 1;
const max_cpus = danos.max_cpus;
pub const ist_stack_size = 16 * 1024;
const max_cpus = config.max_cpus;
pub const ist_stack_size = config.ist_stack_size;
/// One TSS per core (small — kept static). The IST stacks are 16 KiB each, so only
/// the **BSP's** is static: it must exist before the frame allocator does, to catch a
+2 -1
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@@ -1,5 +1,6 @@
const std = @import("std");
const danos = @import("danos");
const config = @import("config");
const arch = @import("arch");
const console = @import("console.zig");
const log = @import("log.zig");
@@ -278,7 +279,7 @@ fn bringUpSecondaries() void {
log.print("\ndanos: bringing up {d} application processor(s)\n", .{cores.len - 1});
const max_wake_attempts = 3; // a core that misses the first INIT-SIPI-SIPI gets retried
for (cores[1..], 1..) |core, index| {
const stack = heap.allocator().alloc(u8, 16 * 1024) catch {
const stack = heap.allocator().alloc(u8, config.kernel_stack_size) catch {
log.print(" cpu apic_id {d}: no stack; skipped\n", .{core.apic_id});
continue;
};
+4 -4
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@@ -18,7 +18,7 @@
//! shared queues.
const std = @import("std");
const danos = @import("danos");
const config = @import("config");
const arch = @import("arch");
const heap = @import("heap.zig");
const sync = @import("sync.zig");
@@ -27,8 +27,8 @@ const sync = @import("sync.zig");
pub const Priority = u3;
const num_priorities = 8;
const stack_size = 16 * 1024; // each task's kernel stack is 16 KiB
const max_tasks = 16; // the maximum number of tasks alive at once is 16 in a static sized pool
const stack_size = config.kernel_stack_size; // each task's kernel stack
const max_tasks = config.max_tasks; // maximum tasks alive at once (static pool)
const State = enum { free, ready, running, blocked };
@@ -69,7 +69,7 @@ pub const PerCpu = struct {
pinned_bitmap: u8 = 0,
};
const max_cpus = danos.max_cpus;
const max_cpus = config.max_cpus;
var cpus = [_]PerCpu{.{}} ** max_cpus;
/// This core's per-CPU state, via the arch layer's GS-base pointer. Valid only once