code lint

This commit is contained in:
Daniel Samson
2026-07-12 19:36:10 +01:00
parent 1cdffe21b1
commit 78582d24d2
2 changed files with 39 additions and 39 deletions
+24 -24
View File
@@ -153,46 +153,46 @@ pub fn writeData(id: u64, status_index: u64, data_index: u64, byte: u8, timeout_
}
pub const Port = enum(u2) {
One,
Two,
one,
two,
/// Command register byte that disables this port.
fn disableCommand(self: Port) u8 {
return switch (self) {
.One => cmd_disable_first_port,
.Two => cmd_disable_second_port,
.one => cmd_disable_first_port,
.two => cmd_disable_second_port,
};
}
/// Command register byte that enables this port (and its clock).
fn enableCommand(self: Port) u8 {
return switch (self) {
.One => cmd_enable_first_port,
.Two => cmd_enable_second_port,
.one => cmd_enable_first_port,
.two => cmd_enable_second_port,
};
}
/// Command register byte that runs this port's interface test.
fn testCommand(self: Port) u8 {
return switch (self) {
.One => cmd_test_first_port,
.Two => cmd_test_second_port,
.one => cmd_test_first_port,
.two => cmd_test_second_port,
};
}
/// Configuration-byte bit that, when set, disables this port's clock.
pub fn clockDisabledBit(self: Port) u8 {
return switch (self) {
.One => configuration_first_port_clock_disabled,
.Two => configuration_second_port_clock_disabled,
.one => configuration_first_port_clock_disabled,
.two => configuration_second_port_clock_disabled,
};
}
/// Configuration-byte bit that, when set, enables this port's interrupt.
pub fn interruptBit(self: Port) u8 {
return switch (self) {
.One => configuration_first_port_interrupt,
.Two => configuration_second_port_interrupt,
.one => configuration_first_port_interrupt,
.two => configuration_second_port_interrupt,
};
}
@@ -200,8 +200,8 @@ pub const Port = enum(u2) {
/// output buffer (makes a byte appear as if it came from the device).
pub fn writeOutputBufferCommand(self: Port) u8 {
return switch (self) {
.One => cmd_write_first_port_output,
.Two => cmd_write_second_port_output,
.one => cmd_write_first_port_output,
.two => cmd_write_second_port_output,
};
}
@@ -210,24 +210,24 @@ pub const Port = enum(u2) {
/// prefix (null); port 2 requires the "write second port input" command.
pub fn deviceInputCommand(self: Port) ?u8 {
return switch (self) {
.One => null,
.Two => cmd_write_second_port_input,
.one => null,
.two => cmd_write_second_port_input,
};
}
/// Controller output-port bit driving this port's clock line.
pub fn outputPortClockBit(self: Port) u8 {
return switch (self) {
.One => output_port_first_port_clock,
.Two => output_port_second_port_clock,
.one => output_port_first_port_clock,
.two => output_port_second_port_clock,
};
}
/// Controller output-port bit driving this port's data line.
pub fn outputPortDataBit(self: Port) u8 {
return switch (self) {
.One => output_port_first_port_data,
.Two => output_port_second_port_data,
.one => output_port_first_port_data,
.two => output_port_second_port_data,
};
}
@@ -235,8 +235,8 @@ pub const Port = enum(u2) {
/// (wired to the port's IRQ line).
pub fn outputPortBufferFullBit(self: Port) u8 {
return switch (self) {
.One => output_port_first_port_output_full,
.Two => output_port_second_port_output_full,
.one => output_port_first_port_output_full,
.two => output_port_second_port_output_full,
};
}
};
@@ -393,9 +393,9 @@ pub const Controller = struct {
/// enabled; the caller should disable it again to keep the bus quiet until
/// device bring-up.
pub fn hasTwoChannels(self: Controller) ?bool {
self.enablePort(.Two);
self.enablePort(.two);
const configuration = self.readConfigurationByte() orelse return null;
return (configuration & Port.Two.clockDisabledBit()) == 0;
return (configuration & Port.two.clockDisabledBit()) == 0;
}
/// Reset the device attached to `port` (device command 0xFF) and wait for