refactor kernel to use device platform discovery

src/kernel/arch/x86_64/cpu.zig

@@ -11,6 +11,7 @@ const idt = @import("idt.zig");
 const paging = @import("paging.zig");
 const serial = @import("serial.zig");
 const apic = @import("apic.zig");
+const ioapic = @import("ioapic.zig");
 const io = @import("io.zig");
 
 /// The saved register/trap frame passed to a fault handler.
@@ -64,9 +65,58 @@ pub fn readCr3() u64 {
 /// Kernel tick rate: 1000 Hz (1 ms), the scheduler's time quantum.
 pub const timer_hz = 1000;
 
-/// Enable the Local APIC, calibrate its timer against the PIT, and start it firing
-/// at `timer_hz` — the kernel's real-time heartbeat. Interrupts still have to be
-/// unmasked with enableInterrupts() to be delivered.
+/// The ACPI PM timer, as a calibration reference (re-exported for the config).
+pub const PmTimer = apic.PmTimer;
+/// A MADT interrupt-source override (re-exported for the config).
+pub const IsoEntry = ioapic.IsoEntry;
+
+/// Discovered platform facts the arch layer needs so it makes no legacy
+/// assumptions — sourced from the device tree + ACPI, passed in by the kernel.
+pub const PlatformConfig = struct {
+    /// Whether the legacy 8259 PIC is present (skip programming it if not).
+    pic_present: bool = true,
+    /// HPET MMIO base (0 = none) — a calibration reference for the timer.
+    hpet_base: u64 = 0,
+    /// The ACPI PM timer, another calibration reference.
+    pm_timer: ?PmTimer = null,
+    /// I/O APIC MMIO base + its first global system interrupt (0 = none).
+    ioapic_base: u64 = 0,
+    ioapic_gsi_base: u32 = 0,
+    /// MADT ISA-IRQ overrides, for I/O APIC routing.
+    overrides: []const IsoEntry = &.{},
+};
+
+/// Apply the discovered platform config. Must run before `startTimer` (the timer
+/// calibration reads `hpet_base`/`pm_timer`) and before any interrupt routing.
+/// Maps + masks the I/O APIC immediately.
+pub fn configurePlatform(cfg: PlatformConfig) void {
+    apic.configure(cfg.pic_present, cfg.hpet_base, cfg.pm_timer);
+    ioapic.configure(cfg.ioapic_base, cfg.ioapic_gsi_base, cfg.overrides);
+    ioapic.init();
+}
+
+/// Point the serial console at the UART ACPI's SPCR table named (MMIO or I/O port).
+pub fn serialReconfigure(is_mmio: bool, addr: u64) void {
+    serial.reconfigure(is_mmio, addr);
+}
+
+/// The reference clock the timer was calibrated against ("cpuid"/"hpet"/…).
+pub fn timerCalibrationSource() []const u8 {
+    return apic.calibrationSource();
+}
+
+/// I/O APIC diagnostics (for boot logging / verification).
+pub fn ioapicEntryCount() u32 {
+    return ioapic.entryCount();
+}
+pub fn ioapicEntryLow(n: u32) u32 {
+    return ioapic.entryLow(n);
+}
+
+/// Enable the Local APIC, calibrate its timer against the best available reference
+/// (see apic.calibrate — no longer the PIT by default), and start it firing at
+/// `timer_hz` — the kernel's real-time heartbeat. Interrupts still have to be
+/// unmasked with enableInterrupts() to be delivered. Run `configurePlatform` first.
 pub fn startTimer() void {
     apic.init();
     apic.calibrate();