acpi: stop parsing AML in the kernel; power management is userspace's
Kernel discovery interpreted the whole DSDT/SSDTs (~0.5 MB -> ~9700 nodes) solely to extract the _S5 sleep type for a kernel-side soft-off — ~1-2s of work on the single-core, pre-scheduler critical path, with nothing to overlap it. The ring-3 acpi service already parses the same blobs and owns S5 end-to-end (reads pm1a_cnt from the FADT, writes SLP_TYP itself; orderly-shutdown tests it). So drop the kernel parse entirely. - all *static*-table parsing stays (MADT/HPET/FADT/MCFG): CPUs, timers, PCIe, and the power register map are still detected from ACPI, not legacy/compat addresses (timer still calibrates via HPET/PM-timer/CPUID, PIT only as last resort) - kernel keeps reboot (FADT reset register + legacy fallbacks — no AML); soft-off is userspace-only now - removed PowerInformation.s5/s3, the kernel AML namespace, aml_stats, amlDeviceCount, and the aml import; power.shutdown/enable/sleepS3 gone - tests: poweroff case retired (S5 covered by orderly-shutdown); discovery drops its S5/AML checks; acpi-parse self-verifies against a device-count floor since there's no kernel count to match
This commit is contained in:
Daniel Samson
+28
-62
@@ -3,11 +3,13 @@
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//! Walks the ACPI tables the firmware left in memory (starting from the RSDP the
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//! bootloader handed us) and translates the static tables into the generic
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//! `device` model, so the kernel enumerates hardware without knowing ACPI is the
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//! source. This is deliberately the *static-table* path: MADT (CPUs / interrupt
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//! controllers), MCFG (PCIe ECAM -> PCI enumeration), HPET (timer), and FADT
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//! (power register map). The DSDT/SSDT bytecode is handed to the `aml` submodule
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//! only to extract the sleep-state (`_Sx`) values for power management; full AML namespace
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//! interpretation is a separate, larger subproject.
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//! source. This is deliberately the *static-table* path, and **only** that: MADT
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//! (CPUs / interrupt controllers), MCFG (PCIe ECAM -> PCI enumeration), HPET
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//! (timer), and FADT (power register map). The DSDT/SSDT bytecode is *not*
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//! interpreted here — the kernel collects the blobs and publishes them on the
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//! acpi-tables node for the ring-3 acpi service to parse (device enumeration and
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//! soft-off). Keeping the ~0.5 MB AML interpretation out of kernel init keeps it
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//! off the single-core critical path (nothing else runs alongside it there).
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//!
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//! ACPI tables live in `.acpi_tables` / `.acpi_nvs` memory, which the kernel
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//! identity-maps, so table addresses are dereferenced directly. PCIe ECAM is MMIO
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@@ -19,7 +21,6 @@ const boot_handoff = @import("boot-handoff");
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const abi = @import("abi");
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const parameters = @import("parameters");
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const device_model = @import("device-model.zig");
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const aml = @import("aml/aml.zig");
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const DeviceTree = device_model.DeviceTree;
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const Hal = device_model.Hal;
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@@ -37,8 +38,11 @@ pub const RegisterAccess = struct {
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}
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};
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/// Everything the power subsystem needs, extracted from the FADT and the AML
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/// sleep packages during discovery. Populated by `discover`, read by `power`.
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/// The power register map, extracted from the FADT during discovery. Populated by
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/// `discover`, read by `power` (kernel reboot). The **sleep-state (`_Sx`) values
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/// live in AML**, which the kernel no longer parses — soft-off (S5) is owned by the
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/// ring-3 acpi service (it re-parses the blobs on the published acpi-tables node and
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/// writes the PM1 control register itself). So this holds only the FADT scalars.
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pub const PowerInformation = struct {
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/// The System Control Interrupt's GSI (FADT SCI_INT) — the line ACPI events
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/// (power button, GPEs) arrive on. Published to the acpi service for M21.
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@@ -54,10 +58,6 @@ pub const PowerInformation = struct {
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reset: RegisterAccess = .{},
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reset_value: u8 = 0,
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reset_supported: bool = false,
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/// SLP_TYP values for S5 (soft off) and S3 (suspend), from the AML sleep-state (`_Sx`)
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/// packages.
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s5: ?aml.SleepType = null,
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s3: ?aml.SleepType = null,
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};
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/// Filled in by `discover`; the power service reads it to reboot/shutdown.
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@@ -141,19 +141,6 @@ const maximum_cpus = parameters.maximum_cpus;
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/// Filled in by `discover` (from the MADT); SMP bring-up reads it to wake the APs.
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pub var cpu_information: CpuInformation = .{};
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/// Integrity/diagnostics for the AML parse. `consumed == total` means the parser
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/// walked every byte of the DSDT/SSDTs without desyncing.
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pub const AmlStats = struct {
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nodes: usize = 0,
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consumed: usize = 0,
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total: usize = 0,
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};
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pub var aml_stats: AmlStats = .{};
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/// The ACPI namespace built from the DSDT/SSDTs, kept for sleep-state (`_Sx`) lookup now and
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/// device enumeration later. Null until `discover` runs successfully.
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pub var namespace: ?aml.Namespace = null;
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/// Physical address of the DSDT the FADT points at, or 0.
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pub var dsdt_physical: u64 = 0;
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@@ -165,8 +152,9 @@ var fadt_physical: u64 = 0;
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var fadt_length: u64 = 0;
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// AML blocks (DSDT + any SSDTs) collected during the table walk, as physical
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// address + length of each table's post-header bytecode. Scanned after the walk
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// for the sleep-state (`_Sx`) packages.
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// address + length of each table's post-header bytecode. The kernel does not
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// interpret them — it publishes them on the acpi-tables node for the ring-3 acpi
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// service to parse (device enumeration + soft-off). See publishAcpiTablesNode.
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var aml_block_physical: [32]u64 = undefined;
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var aml_block_len: [32]usize = undefined;
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var aml_block_count: usize = 0;
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@@ -373,7 +361,7 @@ const Hpet = extern struct {
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/// Discover hardware from the ACPI tables rooted at `rsdp_physical` and populate
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/// `device_tree`. `hal` provides MMIO mapping (for PCIe ECAM) and port I/O. Also parses the
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/// FADT and the AML sleep-state (`_Sx`) packages into `power_information` for the power service.
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/// FADT into `power_information`, and publishes the AML blobs for the ring-3 acpi service.
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pub fn discover(rsdp_physical: u64, memory_regions: []const boot_handoff.MemoryRegion, device_tree: *DeviceTree, hal: Hal) !void {
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if (rsdp_physical == 0) return error.NoRsdp;
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boot_memory_regions = memory_regions;
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@@ -383,8 +371,6 @@ pub fn discover(rsdp_physical: u64, memory_regions: []const boot_handoff.MemoryR
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fadt_physical = 0;
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fadt_length = 0;
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platform_information = .{};
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aml_stats = .{};
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namespace = null;
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dsdt_physical = 0;
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aml_block_count = 0;
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@@ -401,34 +387,20 @@ pub fn discover(rsdp_physical: u64, memory_regions: []const boot_handoff.MemoryR
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try walkRoot(u32, rsdp.root_system_description_table_address, device_tree, hal);
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}
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// Now that the DSDT and any SSDTs are collected, build the AML namespace and
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// read the sleep types from it.
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var blocks: [aml_block_physical.len][]const u8 = undefined;
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for (0..aml_block_count) |i| {
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blocks[i] = @as([*]const u8, @ptrFromInt(boot_handoff.physicalToVirtual(aml_block_physical[i])))[0..aml_block_len[i]];
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}
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const active = blocks[0..aml_block_count];
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if (aml.parse(device_tree.allocator, active)) |pr| {
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namespace = pr.namespace;
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aml_stats = .{ .nodes = namespace.?.nodeCount(), .consumed = pr.consumed, .total = pr.total };
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power_information.s5 = aml.sleepState(&namespace.?, 5);
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power_information.s3 = aml.sleepState(&namespace.?, 3);
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// The namespace's Device objects are no longer folded into the kernel
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// tree (M20.3): the ring-3 acpi service claims the acpi-tables node
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// (published below), re-parses the same blobs, and registers + reports
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// the _HID devices itself. The kernel keeps the namespace only for the
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// \_S5 sleep type above.
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} else |_| {
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// AML parse failed (e.g. out of memory); power stays best-effort with
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// whatever the FADT alone provided.
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}
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// The kernel does **not** interpret the DSDT/SSDTs. Static-table discovery
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// above (MADT/HPET/FADT/MCFG) is all the kernel needs — CPUs, timers, PCIe,
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// and the power register map. The AML bytecode (device enumeration and the
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// sleep-state `_Sx` values for soft-off) is entirely the ring-3 acpi service's
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// job: it claims the acpi-tables node published below, parses the same blobs,
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// and both registers the `_HID` devices and owns S5. Not parsing ~0.5 MB of
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// AML in the kernel keeps boot latency off the critical, single-core path.
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// Publish the acpi-tables node (docs/discovery.md): the AML blobs as
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// memory resources for the acpi service to map and parse in ring 3, a broad
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// io_port grant for the OperationRegion access its interpreter needs, and
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// the SCI for the events track (M21). Exactly one node, one trusted
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// claimant. Kept even when the kernel-side device building (above) retires
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// in M20.3 — the kernel still owns the *static* tables and \_S5.
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// claimant — the sole path by which AML (devices + soft-off) reaches ring 3,
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// now that the kernel keeps only the *static* tables for itself.
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publishAcpiTablesNode(device_tree) catch {};
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}
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@@ -461,12 +433,6 @@ fn publishAcpiTablesNode(device_tree: *DeviceTree) !void {
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if (fadt_physical != 0) _ = node.addResource(.memory, fadt_physical, fadt_length);
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}
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/// The number of Device objects in the namespace built during discovery, or 0.
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pub fn amlDeviceCount() usize {
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if (namespace) |*ns| return aml.deviceCount(ns);
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return 0;
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}
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/// Walk the RSDT (Entry = u32) or XSDT (Entry = u64): validate it, then dispatch
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/// each SDT it points at. A bad individual table is skipped, not fatal.
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fn walkRoot(comptime Entry: type, root_physical: u64, device_tree: *DeviceTree, hal: Hal) !void {
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@@ -502,7 +468,7 @@ fn handleTable(device_tree: *DeviceTree, hal: Hal, sdt_physical: u64) !void {
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} else if (std.mem.eql(u8, &sig, &DMAR)) {
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parseDmar(hal, header);
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} else if (std.mem.eql(u8, &sig, &SSDT)) {
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// Secondary namespace bytecode — collect for the sleep-state (`_Sx`) scan.
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// Secondary namespace bytecode — collect it to publish for the ring-3 parse.
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addAmlBlock(sdt_physical);
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}
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// Any other signature is recognised but left opaque for now.
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@@ -740,8 +706,8 @@ const fadt_x_pm_tmr_blk = 208; // GAS
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const flag_reset_register_supported = 1 << 10;
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const flag_tmr_value_ext = 1 << 8; // PM timer counter is 32-bit (else 24-bit)
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/// FADT -> the power register map (into `power_information`) and the DSDT address, which
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/// is queued for the AML sleep-state (`_Sx`) scan. No AML interpretation happens here.
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/// FADT -> the power register map (into `power_information`) and the DSDT address,
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/// whose bytecode is collected for the ring-3 parse. No AML interpretation here.
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fn parseFadt(header: *const SystemDescriptorTableHeader) void {
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const base: [*]align(1) const u8 = @ptrCast(header);
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const len: usize = header.length;
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@@ -22,13 +22,14 @@ pub const Resource = device_model.Resource;
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pub const ResourceKind = device_model.ResourceKind;
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pub const Hal = device_model.Hal;
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pub const PowerInformation = acpi.PowerInformation;
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pub const AmlStats = acpi.AmlStats;
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pub const PlatformInformation = acpi.PlatformInformation;
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pub const RegisterAccess = acpi.RegisterAccess;
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pub const IsoEntry = acpi.IsoEntry;
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pub const Cpu = acpi.Cpu;
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/// The register map + sleep types discovery extracted, for logging/diagnostics.
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/// The FADT power register map discovery extracted (PM1 control, reset register),
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/// for kernel reboot and diagnostics. Sleep-state values are userspace's (S5 is
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/// owned by the ring-3 acpi service), so they are not here.
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pub fn powerInformation() PowerInformation {
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return acpi.power_information;
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}
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@@ -39,18 +40,6 @@ pub fn platformInformation() PlatformInformation {
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return acpi.platform_information;
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}
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/// AML parse integrity/diagnostics (namespace node count, bytes consumed).
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/// The number of Device objects in the kernel's own AML namespace, or 0 if the
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/// parse produced none — the `acpi-parse` test compares the ring-3 service's
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/// count against this.
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pub fn amlDeviceCount() usize {
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return acpi.amlDeviceCount();
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}
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pub fn amlStats() AmlStats {
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return acpi.aml_stats;
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}
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/// The usable logical processors discovered during enumeration — one entry per
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/// core danos may schedule on, each carrying the Local APIC ID an SMP wake targets.
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/// `len` is the hardware's degree of parallelism: how many tasks *could* run at the
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@@ -92,12 +81,8 @@ pub fn discover(
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}
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/// Restart the machine. Never returns on success; returns only if no reset method
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/// worked (extremely unlikely). Backend-agnostic entry the kernel calls.
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/// worked (extremely unlikely). Backend-agnostic entry the kernel calls. Soft-off
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/// (S5) is not a kernel operation — the ring-3 acpi service owns it (docs/power.md).
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pub fn reboot(hal: Hal) void {
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power.reboot(hal);
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}
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/// Power the machine off (ACPI S5). Never returns on success.
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pub fn shutdown(hal: Hal) void {
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power.shutdown(hal);
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}
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+10
-63
@@ -1,34 +1,17 @@
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//! Machine power control: enter ACPI mode, reboot, and power off (ACPI S5).
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//! Machine reboot: restart via the FADT reset register, with legacy fallbacks.
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//!
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//! Built entirely on the register map `acpi` extracted from the FADT plus the
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//! sleep-state (`_Sx`) types the AML submodule pulled from the DSDT, driven through the
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//! injected `Hal` (port I/O and MMIO). Nothing here is x86-specific beyond the
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//! well-known legacy reset fallbacks, which are guarded behind the ACPI methods.
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//!
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//! S3 (suspend-to-RAM) is stubbed: it needs a wake trampoline and device
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//! re-initialisation, a milestone of its own.
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//! Built on the register map `acpi` extracted from the FADT, driven through the
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//! injected `Hal` (port I/O and MMIO). Soft-off (ACPI S5) and suspend (S3) are
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//! **not** here: they need the AML sleep-state (`_Sx`) values, which the kernel no
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//! longer parses — the ring-3 acpi service owns power management (it re-parses the
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//! blobs and writes the PM1 control register itself). See docs/power.md. Reboot
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//! stays in the kernel because it needs no AML — only the FADT reset register and
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//! the well-known legacy fallbacks — so it survives as a last-resort restart.
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const acpi = @import("acpi.zig");
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const device_model = @import("device-model.zig");
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const Hal = device_model.Hal;
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const slp_en: u32 = 1 << 13; // SLP_EN: writing 1 triggers the sleep transition
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const sci_en: u32 = 1 << 0; // SCI_EN in PM1 control: set once ACPI mode is active
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/// Switch the platform into ACPI mode if it isn't already, so the PM1 control
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/// register is live. A no-op when the firmware exposes no SMI command port (ACPI
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/// already enabled, as under QEMU/OVMF) — we still verify SCI_EN first.
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pub fn enable(hal: Hal) void {
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const pi = acpi.power_information;
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if (!pi.pm1a_cnt.present()) return;
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if (readRegister(hal, pi.pm1a_cnt) & sci_en != 0) return; // already in ACPI mode
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if (pi.smi_cmd == 0 or pi.acpi_enable == 0) return; // no way to switch; assume fine
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hal.pioWrite(1, pi.smi_cmd, pi.acpi_enable);
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var spins: usize = 0;
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while (readRegister(hal, pi.pm1a_cnt) & sci_en == 0 and spins < 1_000_000) : (spins += 1) {}
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}
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/// Restart the machine. Tries the ACPI reset register first, then the two legacy
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/// fallbacks. Returns only if every method failed (very unlikely).
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pub fn reboot(hal: Hal) void {
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@@ -48,42 +31,6 @@ pub fn reboot(hal: Hal) void {
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delay();
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}
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/// Power the machine off via ACPI S5. Requires the soft-off (`_S5`) sleep type; if
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/// it wasn't found in the AML, there is nothing safe to do and this returns.
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pub fn shutdown(hal: Hal) void {
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enable(hal);
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const pi = acpi.power_information;
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const s5 = pi.s5 orelse return;
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if (pi.pm1a_cnt.present()) {
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writeRegister(hal, pi.pm1a_cnt, sleepValue(s5.slp_typ_a));
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}
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if (pi.pm1b_cnt.present()) {
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writeRegister(hal, pi.pm1b_cnt, sleepValue(s5.slp_typ_b));
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}
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delay();
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}
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/// S3 suspend-to-RAM — not implemented (needs a wake path + device re-init).
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pub fn sleepS3(hal: Hal) error{Unsupported}!void {
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_ = hal;
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return error.Unsupported;
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}
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/// The PM1 control write that requests sleep type `slp_typ`: SLP_TYP in bits
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/// [12:10], SLP_EN in bit 13.
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fn sleepValue(slp_typ: u8) u32 {
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return (@as(u32, slp_typ & 0x7) << 10) | slp_en;
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}
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fn readRegister(hal: Hal, register: acpi.RegisterAccess) u32 {
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if (register.mmio) {
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const p: *align(1) volatile u32 = @ptrFromInt(hal.mapMmio(register.address, 4, true));
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return p.*;
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}
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return hal.pioRead(register.width, @intCast(register.address));
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}
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fn writeRegister(hal: Hal, register: acpi.RegisterAccess, value: u32) void {
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if (register.mmio) {
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const p: *align(1) volatile u32 = @ptrFromInt(hal.mapMmio(register.address, 4, true));
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@@ -93,8 +40,8 @@ fn writeRegister(hal: Hal, register: acpi.RegisterAccess, value: u32) void {
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}
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}
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/// A short busy-wait so a reset/power-off takes effect before we fall through to
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/// the next method. The empty asm is an architecture-neutral barrier that keeps the loop
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/// A short busy-wait so a reset takes effect before we fall through to the next
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/// method. The empty asm is an architecture-neutral barrier that keeps the loop
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/// from being optimised away.
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fn delay() void {
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var i: usize = 0;
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