Built paging / the kernel's own page tables (with a TSS+IST)

src/arch/x86_64/idt.zig

@@ -7,6 +7,7 @@
 //! interrupts (the APIC, timer, keyboard) come later.
 
 const gdt = @import("gdt.zig");
+const tss = @import("tss.zig");
 
 /// The register + trap frame the ISR stubs build on the stack, laid out so the
 /// lowest address (where RSP points when we call the handler) is the first field.
@@ -106,6 +107,9 @@ pub fn init() void {
         const stub = @extern(*const anyopaque, .{ .name = std.fmt.comptimePrint("isr{d}", .{vector}) });
         setGate(vector, @intFromPtr(stub));
     }
+    // Run the double-fault handler (vector 8) on IST1: a #DF usually means the
+    // current stack is unusable, so it needs a guaranteed-good one. See tss.zig.
+    idt[8].ist = tss.double_fault_ist;
     const descriptor = Descriptor{
         .limit = @sizeOf(@TypeOf(idt)) - 1,
         .base = @intFromPtr(&idt),