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Cross-architecture test suite

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daniel
2026-07-03 12:39:26 +01:00
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docs/arch.md
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@@ -63,12 +63,16 @@ There are really two independent questions, and it's worth not conflating them:
- **`src/arch/x86_64/cpu.zig`** — the `arch` module root. Exposes `halt()` (see
[halting.md](halting.md)), `init()` (bring up the descriptor tables),
`setFaultHandler`, `readCr2`, and the `CpuState` trap frame. Paging will join it
here as the kernel grows.
- **`src/arch/x86_64/gdt.zig`** / **`idt.zig`** — the GDT and IDT plus CPU-exception
handling (see [interrupts.md](interrupts.md)).
- **`src/arch/x86_64/isr.s`** — the exception stubs and the `lgdt`/`lidt` load
helpers, in real assembly because Zig inline asm can't express them.
`enablePaging()`, `setFaultHandler`, `readCr2`/`readCr3`, and the `CpuState`
trap frame.
- **`src/arch/x86_64/gdt.zig`** / **`idt.zig`** / **`tss.zig`** — the GDT, IDT and
TSS plus CPU-exception handling (see [interrupts.md](interrupts.md)).
- **`src/arch/x86_64/paging.zig`** — the kernel's page tables (see
[paging.md](paging.md)).
- **`src/arch/x86_64/serial.zig`** — the COM1 UART, the kernel's machine-readable
log channel (see [testing.md](testing.md)).
- **`src/arch/x86_64/isr.s`** — the exception stubs and the `lgdt`/`lidt`/`ltr`
load helpers, in real assembly because Zig inline asm can't express them.
- **`src/arch/x86_64/linker.ld`** — the kernel link layout (fixed low load
address, one PT_LOAD per permission set).