pci-bus registers and reports what it scans (M19.2)
Each function is registered under the bridge with the config-space slice and BARs sized by the same all-ones probe the kernel uses — byte-for-byte equal descriptors, so the idempotent register returns the kernel's existing node ids during coexistence instead of duplicating the tree. The bridge gained the 16-bit io_port aperture that functions' I/O BARs need to pass containment. Reports carry the registered device_id, and the pci-scan scenario drills a forced restart: kill the enumerator after its reports, watch the respawn re-scan, and assert the broker's PCI node count never grew. The usb-restart test trigger is pinned to the xHCI reporter (pci-bus racing it to two reports used to steal the kill). Harness hardening: failing cases preserve their serial logs; the heavy scenarios run at 150s.
This commit is contained in:
@@ -553,6 +553,9 @@ fn parseMcfg(device_tree: *DeviceTree, hal: Hal, header: *const SystemDescriptor
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_ = bridge.addResource(.memory, alloc.base_address, bus_count << 20);
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_ = bridge.addResource(.bus_range, alloc.start_bus, bus_count);
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addBridgeApertures(bridge);
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// The bridge decodes the whole 16-bit I/O space toward its bus — the
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// window functions' I/O BARs must register-contain within (M19.2).
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_ = bridge.addResource(.io_port, 0, 1 << 16);
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try enumeratePci(device_tree, bridge, hal, alloc.*);
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}
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@@ -22,8 +22,10 @@ fn writeLine(comptime fmt: []const u8, arguments: anytype) void {
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var bridge_id: u64 = protocol.no_device;
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var ecam_base: usize = 0;
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var ecam_physical: u64 = 0;
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var start_bus: u64 = 0;
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var bus_count: u64 = 0;
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var manager_handle: runtime.ipc.Handle = 0;
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/// One aligned 32-bit read from a function's configuration space.
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fn configRead(bus: u64, dev: u64, function: u64, offset: u64) u32 {
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@@ -32,6 +34,25 @@ fn configRead(bus: u64, dev: u64, function: u64, offset: u64) u32 {
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return register.*;
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}
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fn configWrite(bus: u64, dev: u64, function: u64, offset: u64, value: u32) void {
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const address = ecam_base + (((bus - start_bus) << 20) | (dev << 15) | (function << 12) | offset);
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const register: *volatile u32 = @ptrFromInt(address);
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register.* = value;
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}
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fn configRead16(bus: u64, dev: u64, function: u64, offset: u64) u16 {
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const word = configRead(bus, dev, function, offset & ~@as(u64, 3));
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return @truncate(word >> @intCast((offset & 3) * 8));
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}
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fn configWrite16(bus: u64, dev: u64, function: u64, offset: u64, value: u16) void {
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const aligned = offset & ~@as(u64, 3);
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const shift: u5 = @intCast((offset & 3) * 8);
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const word = configRead(bus, dev, function, aligned);
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const mask = @as(u32, 0xFFFF) << shift;
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configWrite(bus, dev, function, aligned, (word & ~mask) | (@as(u32, value) << shift));
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}
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/// Claim the bridge, map the ECAM, hello the manager, then scan.
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fn initialise(endpoint: runtime.ipc.Handle) bool {
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_ = endpoint;
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@@ -64,6 +85,7 @@ fn initialise(endpoint: runtime.ipc.Handle) bool {
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};
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start_bus = bus_range.start;
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bus_count = bus_range.len;
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ecam_physical = descriptor.resources[0].start;
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ecam_base = device.mmioMap(bridge_id, 0) orelse {
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_ = runtime.system.write("pci-bus: ECAM mmio_map failed\n");
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return false;
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@@ -90,6 +112,7 @@ fn initialise(endpoint: runtime.ipc.Handle) bool {
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_ = runtime.system.write("pci-bus: hello refused\n");
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return false;
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}
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manager_handle = h;
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scan();
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return true;
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@@ -115,12 +138,92 @@ fn scan() void {
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const class_revision = configRead(bus, dev, function, 0x08);
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found += 1;
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writeLine("pci-bus: {d}:{d}.{d} class 0x{x:0>6}\n", .{ bus, dev, function, class_revision >> 8 });
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registerAndReport(bus, dev, function, class_revision >> 8);
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}
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}
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}
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writeLine("pci-bus: {d} functions found\n", .{found});
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}
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/// Register one function under the bridge and report it to the manager. The
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/// descriptor mirrors the kernel's own recording byte for byte — config slice
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/// as resource 0, then the sized BARs — so during coexistence the idempotent
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/// device_register (M19.0) returns the kernel's existing node id rather than
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/// growing a duplicate, and the report carries the id drivers already use.
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fn registerAndReport(bus: u64, dev: u64, function: u64, class_triple: u32) void {
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var descriptor = std.mem.zeroes(device.DeviceDescriptor);
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descriptor.class = @intFromEnum(device.DeviceClass.pci_device);
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descriptor.pci_class = class_triple;
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descriptor.resources[0] = .{
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.kind = @intFromEnum(device.ResourceKind.memory),
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.start = ecam_physical + (((bus - start_bus) << 20) | (dev << 15) | (function << 12)),
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.len = 4096,
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};
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descriptor.resource_count = 1;
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// The standard BAR-sizing probe, exactly as the kernel does it: decode off,
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// write all-ones, read the writable mask back, restore. Header type 0 only.
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const header_type = (configRead(bus, dev, function, 0x0C) >> 16) & 0x7F;
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if (header_type == 0) {
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const command = configRead16(bus, dev, function, 0x04);
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configWrite16(bus, dev, function, 0x04, command & ~@as(u16, 0b11));
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var i: u64 = 0;
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while (i < 6) : (i += 1) {
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if (descriptor.resource_count >= 8) break;
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const off = 0x10 + i * 4;
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const original = configRead(bus, dev, function, off);
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if (original == 0) continue;
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const slot: usize = @intCast(descriptor.resource_count);
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if (original & 1 != 0) {
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configWrite(bus, dev, function, off, 0xFFFF_FFFF);
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const readback = configRead(bus, dev, function, off);
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configWrite(bus, dev, function, off, original);
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const mask = readback & 0xFFFF_FFFC;
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const size: u32 = if (mask == 0) 0 else (~mask +% 1) & 0xFFFF;
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descriptor.resources[slot] = .{ .kind = @intFromEnum(device.ResourceKind.io_port), .start = original & 0xFFFF_FFFC, .len = size };
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descriptor.resource_count += 1;
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} else if ((original >> 1) & 0x3 == 2) {
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const original_high = configRead(bus, dev, function, off + 4);
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configWrite(bus, dev, function, off, 0xFFFF_FFFF);
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configWrite(bus, dev, function, off + 4, 0xFFFF_FFFF);
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const lo = configRead(bus, dev, function, off);
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const hi = configRead(bus, dev, function, off + 4);
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configWrite(bus, dev, function, off, original);
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configWrite(bus, dev, function, off + 4, original_high);
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const readback = (@as(u64, hi) << 32) | (lo & 0xFFFF_FFF0);
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const size: u64 = if (readback == 0) 0 else ~readback +% 1;
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descriptor.resources[slot] = .{ .kind = @intFromEnum(device.ResourceKind.memory), .start = (@as(u64, original_high) << 32) | (original & 0xFFFF_FFF0), .len = size };
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descriptor.resource_count += 1;
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i += 1; // consumed the high half
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} else {
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configWrite(bus, dev, function, off, 0xFFFF_FFFF);
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const readback = configRead(bus, dev, function, off);
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configWrite(bus, dev, function, off, original);
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const mask = readback & 0xFFFF_FFF0;
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const size: u32 = if (mask == 0) 0 else ~mask +% 1;
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descriptor.resources[slot] = .{ .kind = @intFromEnum(device.ResourceKind.memory), .start = original & 0xFFFF_FFF0, .len = size };
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descriptor.resource_count += 1;
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}
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}
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configWrite16(bus, dev, function, 0x04, command);
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}
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const registered = device.register(bridge_id, &descriptor) orelse {
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writeLine("pci-bus: register refused for {d}:{d}.{d}\n", .{ bus, dev, function });
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return;
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};
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const report = protocol.ChildAdded{
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.parent = bridge_id,
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.bus_address = (bus << 8) | (dev << 3) | function,
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.identity = class_triple,
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.device_id = registered,
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};
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var reply: [protocol.message_maximum]u8 = undefined;
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_ = runtime.ipc.call(manager_handle, std.mem.asBytes(&report), &reply) catch {
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writeLine("pci-bus: child report for {d}:{d}.{d} failed\n", .{ bus, dev, function });
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};
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}
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fn onMessage(message: []const u8, reply: []u8, sender: u32, capability: ?runtime.ipc.Handle) usize {
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_ = message;
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_ = reply;
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+37
-3
@@ -1836,13 +1836,14 @@ fn pciScanTest(boot_information: *const BootInformation) void {
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while (i < rd.count) : (i += 1) {
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const item = rd.entry(i) orelse continue;
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if (!eql(item.name, "device-manager")) continue;
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manager = process.spawnProcessSupervised(item.blob, 4, &.{"device-manager"}, scheduler.currentId(), null) catch 0;
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manager = process.spawnProcessSupervised(item.blob, 4, &.{ "device-manager", "test-pci-restart" }, scheduler.currentId(), null) catch 0;
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break;
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}
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check("device-manager spawned", manager != 0);
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check("device-manager spawned (test-pci-restart mode)", manager != 0);
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// First scan: the ring-3 count equals the kernel's.
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scheduler.setPriority(1);
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const deadline = architecture.millis() + 15000;
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var deadline = architecture.millis() + 15000;
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var seen = false;
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while (architecture.millis() < deadline and !seen) {
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if (process.write_len >= marker.len and eql(process.write_buffer[0..marker.len], marker)) seen = true;
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@@ -1850,6 +1851,39 @@ fn pciScanTest(boot_information: *const BootInformation) void {
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}
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scheduler.setPriority(4);
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check("the ring-3 scan found exactly the kernel's function count", seen);
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// The restart drill: the manager kills pci-bus after its reports; the
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// respawn re-claims, re-scans, and re-registers.
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const restart_marker = "device-manager: restarting pci-bus";
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scheduler.setPriority(1);
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deadline = architecture.millis() + 15000;
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var restarted = false;
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while (architecture.millis() < deadline and !restarted) {
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if (process.write_len >= restart_marker.len and eql(process.write_buffer[0..restart_marker.len], restart_marker)) restarted = true;
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scheduler.yield();
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}
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scheduler.setPriority(4);
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check("the manager restarted pci-bus", restarted);
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scheduler.setPriority(1);
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deadline = architecture.millis() + 15000;
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seen = false;
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while (architecture.millis() < deadline and !seen) {
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if (process.write_len >= marker.len and eql(process.write_buffer[0..marker.len], marker)) seen = true;
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scheduler.yield();
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}
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scheduler.setPriority(4);
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check("the respawned scan reported the same count", seen);
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// No duplicates: the registrations deduped against the kernel's own nodes
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// on the first pass, and against themselves on the second.
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var after: [64]device_abi.DeviceDescriptor = undefined;
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const m = @min(devices_broker.enumerate(&after), after.len);
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var after_count: u32 = 0;
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for (after[0..m]) |d| {
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if (d.class == @intFromEnum(device_abi.DeviceClass.pci_device)) after_count += 1;
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}
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check("no duplicate PCI nodes after register + restart + re-register", after_count == kernel_count);
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result();
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}
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@@ -108,6 +108,7 @@ var manager_endpoint: runtime.ipc.Handle = 0;
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var test_restart_mode = false;
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var test_usb_restart_mode = false;
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var test_usb_killed = false;
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var test_pci_restart_mode = false;
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var test_kill_pid: u32 = 0;
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var test_kill_due_ns: u64 = 0;
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@@ -400,13 +401,32 @@ fn onChildAdded(message: []const u8, reply: []u8, sender: u32) usize {
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}
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const report_reply = protocol.ReportReply{ .status = status };
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@memcpy(reply[0..@sizeOf(protocol.ReportReply)], std.mem.asBytes(&report_reply));
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if (test_pci_restart_mode and !test_usb_killed) {
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if (driverByProcess(sender)) |driver| {
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if (std.mem.eql(u8, driver.name(), "pci-bus") and childCountOf(sender) >= 3) {
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// The pci restart drill: kill the enumerator after it has
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// reported; the respawn must re-register without duplicates
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// (M19.0 idempotence, proven end to end by pci-scan).
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test_usb_killed = true;
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test_kill_pid = sender;
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test_kill_due_ns = system.clock() + 1_000_000_000;
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_ = system.timerOnce(manager_endpoint, 1100);
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}
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}
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}
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if (test_usb_restart_mode and !test_usb_killed and childCountOf(sender) >= 2) {
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// Delayed, not immediate: the device-list scenario's subscriber needs a
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// window to enumerate and subscribe before the events start.
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test_usb_killed = true;
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test_kill_pid = sender;
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test_kill_due_ns = system.clock() + 2_000_000_000;
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_ = system.timerOnce(manager_endpoint, 2100);
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// Only the xHCI reporter is the drill's victim — pci-bus also reports
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// now, and whichever finishes second must not trigger the kill.
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if (driverByProcess(sender)) |driver| {
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if (std.mem.eql(u8, driver.name(), "usb-xhci-bus")) {
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// Delayed, not immediate: the device-list scenario's subscriber
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// needs a window to enumerate and subscribe before the events.
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test_usb_killed = true;
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test_kill_pid = sender;
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test_kill_due_ns = system.clock() + 2_000_000_000;
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_ = system.timerOnce(manager_endpoint, 2100);
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}
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}
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}
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return @sizeOf(protocol.ReportReply);
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}
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@@ -476,6 +496,7 @@ pub fn main(init: runtime.process.Init) void {
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if (init.arguments.get(1)) |mode| {
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test_restart_mode = std.mem.eql(u8, mode, "test-restart");
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test_usb_restart_mode = std.mem.eql(u8, mode, "test-usb-restart");
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test_pci_restart_mode = std.mem.eql(u8, mode, "test-pci-restart");
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}
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runtime.service.run(protocol.message_maximum, .{
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.service = .device_manager,
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Block a user