Merge feat/power-events: ACPI events + system power (M21)
The QMP harness channel, the SCI + power button published from ring 3, Notify/GPE dispatch in the AML interpreter, and orderly shutdown — init's M17 stop cascade into a ring-3 S5 write. Proven by injecting a real ACPI power-button event; QEMU powers off through the whole chain. # Conflicts: # system/services/init/init.zig
This commit is contained in:
Daniel Samson
+323
-32
@@ -4,13 +4,11 @@
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//! grant, a broad irq window, the SCI), and runs the **shared AML module** in
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//! ring 3 — the same parser and interpreter the kernel uses.
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//!
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//! M20.2 (this increment): after parsing, walk the namespace and, for each
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//! present Device with a hardware id (`_HID`), evaluate its current resource
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//! settings (`_CRS`) through a ring-3 `Hal` (port I/O over the claimed node),
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//! register it under the acpi-tables node (its I/O ports and IRQs contained by
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//! the node's broad grants), and report it to the device manager with its
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//! EISA-decoded hid as identity. Matching those reports to drivers (ps2-bus)
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//! and retiring the kernel's own device build follow in M20.3.
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//! It also owns the **event side** (M21): it registers the domain-named `.power`
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//! service, binds the SCI (System Control Interrupt), and on a power-button
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//! fixed event publishes `power_button` to subscribers — and on init's request
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//! writes S5 to power the machine off. The device discovery (M20) and the event
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//! handling both run in one `runtime.service.run` loop.
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const std = @import("std");
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const runtime = @import("runtime");
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@@ -18,6 +16,7 @@ const aml = @import("aml");
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const acpi_ids = @import("acpi-ids");
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const device = runtime.device;
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const protocol = runtime.device_manager_protocol;
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const power = runtime.power_protocol;
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/// AML opcode/prefix bytes by name (`zero_opcode`, `byte_prefix`, …) — so the `_HID`
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/// integer decode names the opcodes instead of bare 0x0A/0x0B/… (docs/coding-standards.md).
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const opcodes = aml.opcodes;
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@@ -31,6 +30,43 @@ fn writeLine(comptime fmt: []const u8, arguments: anytype) void {
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// window — the Hal routes every port access through this one claim.
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var node_id: u64 = 0;
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var io_resource_index: u64 = 0;
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// The SCI's irq resource index on the node (the len-1 irq, distinct from the
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// broad [0,256) window), for irqBind / irqAck.
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var sci_resource_index: u64 = 0;
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var has_sci = false;
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// PM1 event/control and GPE register ports, read from the FADT copy the kernel
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// publishes on the node (M21). Port 0 means absent.
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var pm1a_evt: u16 = 0;
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var pm1b_evt: u16 = 0;
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var pm1_evt_len: u8 = 0;
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var pm1a_cnt: u16 = 0;
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var pm1b_cnt: u16 = 0;
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var gpe0_blk: u16 = 0;
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var gpe0_len: u8 = 0;
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var gpe1_blk: u16 = 0;
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var gpe1_len: u8 = 0;
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var smi_cmd: u16 = 0;
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var acpi_enable_value: u8 = 0;
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var s5_slp_typ_a: u8 = 0;
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var s5_slp_typ_b: u8 = 0;
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var s5_valid = false;
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// PM1 event-register bits (ACPI): PWRBTN in the status/enable word is bit 8;
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// the control word's SCI_EN is bit 0; SLP_EN is bit 13.
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const pwrbtn_bit: u16 = 1 << 8;
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const sci_en_bit: u32 = 1 << 0;
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const slp_en: u32 = 1 << 13;
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// The `.power` subscribers: endpoints handed over as capabilities, each
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// receiving events as buffered messages. Dropped on a failed send. The
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// subscriber's task id is kept too — a shutdown request is honored only from a
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// subscriber (init subscribes; a stray process does not), the soft gate that
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// stands in for "only the system supervisor may power off" without hardcoding
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// a pid the kernel's idle tasks would have taken.
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const maximum_subscribers = 8;
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var subscribers: [maximum_subscribers]?runtime.ipc.Handle = .{null} ** maximum_subscribers;
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var subscriber_tasks: [maximum_subscribers]u32 = .{0} ** maximum_subscribers;
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// Pass-1 registration record (see main): what pass 2 reports.
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const Registered = struct { hid: [8]u8 = .{0} ** 8, hid_len: usize = 0, device_id: u64 = 0, resource_count: u64 = 0 };
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@@ -85,22 +121,34 @@ pub fn main(init: runtime.process.Init) void {
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return;
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}
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// Map each memory resource (an AML blob) and note the io_port resource.
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// Map the node's resources: the AML blobs (bytecode), the FADT (intact
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// "FACP" header — decision 3), the io_port grant, and the SCI irq.
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var blocks: [8][]const u8 = undefined;
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var block_count: usize = 0;
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var found_io = false;
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var fadt: ?[]const u8 = null;
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for (node.resources[0..@intCast(node.resource_count)], 0..) |resource, index| {
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if (resource.kind == @intFromEnum(device.ResourceKind.io_port) and !found_io) {
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io_resource_index = index;
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found_io = true;
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continue;
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}
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if (resource.kind == @intFromEnum(device.ResourceKind.irq) and resource.len == 1) {
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sci_resource_index = index;
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has_sci = true;
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continue;
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}
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if (resource.kind != @intFromEnum(device.ResourceKind.memory)) continue;
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const base = device.mmioMap(node_id, index) orelse continue;
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const pointer: [*]const u8 = @ptrFromInt(base);
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blocks[block_count] = pointer[0..@intCast(resource.len)];
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const bytes = pointer[0..@intCast(resource.len)];
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if (bytes.len >= 4 and std.mem.eql(u8, bytes[0..4], "FACP")) {
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fadt = bytes;
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continue;
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}
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if (block_count == blocks.len) continue;
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blocks[block_count] = bytes;
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block_count += 1;
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if (block_count == blocks.len) break;
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}
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if (block_count == 0) {
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_ = runtime.system.write("/system/services/acpi: no AML blobs on the node\n");
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@@ -124,29 +172,45 @@ pub fn main(init: runtime.process.Init) void {
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while (true) runtime.system.sleep(1000);
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}
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// Register + report the present _HID devices (M20.2).
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var arena = std.heap.ArenaAllocator.init(runtime.allocator());
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var interpreter = aml.Interpreter.init(&namespace, .{
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// Register + report the present _HID devices (M20), then set up the power
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// event side (M21), then serve — all in one harness loop. The interpreter
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// and namespace outlive this frame (static), so the harness callbacks can
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// reach them.
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interpreter_arena = std.heap.ArenaAllocator.init(runtime.allocator());
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persistent_namespace = namespace;
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global_interpreter = aml.Interpreter.init(&persistent_namespace, .{
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.mapMmio = halMapMmio,
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.pioRead = halPioRead,
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.pioWrite = halPioWrite,
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}, arena.allocator());
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}, interpreter_arena.allocator());
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// Pass 1: register every present _HID device under acpi-tables, remembering
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// each (hid, device id). Pass 2: report them all. Registering before any
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// report reaches the manager means a driver it spawns on the first report
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// already sees the whole set (no keyboard-before-mouse race for ps2-bus).
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readFadt(fadt);
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s5_valid = readSleepS5(&persistent_namespace);
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runtime.service.run(power.message_maximum, .{
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.service = .power,
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.init = onInit,
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.on_message = onMessage,
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.on_notification = onNotification,
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});
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}
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// Static so the harness callbacks (which run after main's stack frame is gone)
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// can reach the namespace and interpreter.
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var persistent_namespace: aml.Namespace = undefined;
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var global_interpreter: aml.Interpreter = undefined;
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var interpreter_arena: std.heap.ArenaAllocator = undefined;
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/// Startup under the harness: register + report the discovered devices to the
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/// manager (M20), then enable ACPI mode and arm the power button (M21).
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fn onInit(endpoint: runtime.ipc.Handle) bool {
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registered_count = 0;
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walkDevices(namespace.root, &interpreter);
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walkDevices(persistent_namespace.root, &global_interpreter);
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const manager = runtime.ipc.lookup(.device_manager);
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var i: usize = 0;
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while (i < registered_count) : (i += 1) {
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const entry = registered[i];
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// Append the _HID's human-readable name when it is a known standard PnP/ACPI
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// id (e.g. PNP0303 -> "PS/2 Keyboard"), so the boot log says what each
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// reported device actually is. The description trails the existing fields so
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// the acpi-report/acpi-ps2 matchers still see "<hid> (device N, M resources)".
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const hid = entry.hid[0..entry.hid_len];
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const desc = acpi_ids.description(hid);
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if (desc.len != 0)
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@@ -154,12 +218,7 @@ pub fn main(init: runtime.process.Init) void {
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else
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writeLine("/system/services/acpi: reported {s} (device {d}, {d} resources)\n", .{ hid, entry.device_id, entry.resource_count });
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if (manager) |h| {
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var report = protocol.ChildAdded{
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.parent = node_id,
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.bus_address = entry.device_id,
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.identity = 0,
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.device_id = entry.device_id,
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};
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var report = protocol.ChildAdded{ .parent = node_id, .bus_address = entry.device_id, .identity = 0, .device_id = entry.device_id };
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@memcpy(report.hid[0..entry.hid_len], entry.hid[0..entry.hid_len]);
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var reply: [protocol.message_maximum]u8 = undefined;
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_ = runtime.ipc.call(h, std.mem.asBytes(&report), &reply) catch {};
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@@ -167,9 +226,241 @@ pub fn main(init: runtime.process.Init) void {
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}
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writeLine("/system/services/acpi: reported {d} device(s) to the manager\n", .{registered_count});
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// Stay resident: the claim holds, and the service is here to grow into the
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// supervised discoverer (M20.3, then the M21 event side on the SCI).
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while (true) runtime.system.sleep(1000);
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armPowerButton(endpoint);
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return true;
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}
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// --- power event side (M21) ---------------------------------------------------
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/// Read the PM1 event/control and GPE register ports plus the SMI enable pair
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/// from the FADT copy on the node. Offsets are from the FADT table start (the
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/// SDT header is the first 36 bytes). Prefers the 32-bit port fields; QEMU's
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/// FADT populates them.
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fn readFadt(fadt: ?[]const u8) void {
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const f = fadt orelse {
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_ = runtime.system.write("acpi: no FADT on the node — power events off\n");
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return;
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};
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smi_cmd = @truncate(rd32(f, 48));
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acpi_enable_value = f[52];
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pm1a_evt = @truncate(rd32(f, 56));
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pm1b_evt = @truncate(rd32(f, 60));
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pm1a_cnt = @truncate(rd32(f, 64));
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pm1b_cnt = @truncate(rd32(f, 68));
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gpe0_blk = @truncate(rd32(f, 80));
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gpe1_blk = @truncate(rd32(f, 84));
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pm1_evt_len = if (f.len > 88) f[88] else 4;
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gpe0_len = if (f.len > 92) f[92] else 0;
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gpe1_len = if (f.len > 93) f[93] else 0;
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}
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fn readSleepS5(ns: *aml.Namespace) bool {
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const st = aml.sleepState(ns, 5) orelse return false;
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s5_slp_typ_a = st.slp_typ_a;
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s5_slp_typ_b = st.slp_typ_b;
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return true;
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}
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/// Enable ACPI mode if the firmware isn't already in it, then bind the SCI and
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/// set PWRBTN_EN so the power button raises an interrupt we can see.
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fn armPowerButton(endpoint: runtime.ipc.Handle) void {
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if (pm1a_cnt != 0 and (halPioRead(2, pm1a_cnt) & sci_en_bit) == 0 and smi_cmd != 0) {
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// Switch to ACPI mode: write ACPI_ENABLE to the SMI command port, then
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// spin (bounded) until SCI_EN latches.
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halPioWrite(1, smi_cmd, acpi_enable_value);
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var tries: u32 = 0;
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while (tries < 1000 and (halPioRead(2, pm1a_cnt) & sci_en_bit) == 0) : (tries += 1) {
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runtime.system.sleep(1);
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}
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}
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if (!has_sci) {
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_ = runtime.system.write("acpi: no SCI resource — power button unavailable\n");
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return;
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}
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if (!device.irqBind(node_id, sci_resource_index, endpoint)) {
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_ = runtime.system.write("acpi: SCI irq_bind failed\n");
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return;
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}
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// PWRBTN_EN lives in the PM1 enable register at evt_blk + evt_len/2.
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if (pm1a_evt != 0) {
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const en_port = pm1a_evt + pm1_evt_len / 2;
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halPioWrite(2, en_port, @as(u16, @truncate(halPioRead(2, en_port))) | pwrbtn_bit);
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}
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if (pm1b_evt != 0) {
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const en_port = pm1b_evt + pm1_evt_len / 2;
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halPioWrite(2, en_port, @as(u16, @truncate(halPioRead(2, en_port))) | pwrbtn_bit);
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}
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_ = runtime.system.write("acpi: power button armed\n");
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}
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/// The SCI fired. Read PM1 status; a set PWRBTN_STS is the power button — clear
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/// it (write-1), publish, log. Any other set status is cleared and logged
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/// (GPE/Notify dispatch is M21.2). Always re-arm the line.
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fn onSci() void {
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var handled = false;
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inline for (.{ pm1a_evt, pm1b_evt }) |evt_port| {
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if (evt_port != 0) {
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const sts: u16 = @truncate(halPioRead(2, evt_port));
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if (sts & pwrbtn_bit != 0) {
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halPioWrite(2, evt_port, pwrbtn_bit); // write-1-to-clear
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handled = true;
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} else if (sts != 0) {
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halPioWrite(2, evt_port, sts); // clear whatever else latched
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}
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}
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}
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if (handled) {
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_ = runtime.system.write("power: button pressed\n");
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publishButton();
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}
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handleGpe();
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_ = device.irqAck(node_id, sci_resource_index);
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}
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/// General-purpose events: for each set+enabled GPE bit, evaluate its `\_GPE`
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/// handler method (`_Lxx` level / `_Exx` edge), drain the Notify queue the
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/// method produced, and publish an event per notified device. Then clear the
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/// status bit. QEMU raises no GPEs on this config, so this path is exercised by
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/// host unit tests (docs/m21-plan.md decision 5); on real hardware it carries
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/// battery/AC/lid. The embedded controller's `_Qxx` queries are out of scope.
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fn handleGpe() void {
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handleGpeBlock(gpe0_blk, gpe0_len, 0);
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handleGpeBlock(gpe1_blk, gpe1_len, gpe0_len * 4);
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}
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fn handleGpeBlock(blk: u16, len: u8, gpe_base: u32) void {
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if (blk == 0 or len == 0) return;
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const status_bytes = len / 2; // status half, then enable half
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var byte_index: u8 = 0;
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while (byte_index < status_bytes) : (byte_index += 1) {
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const sts: u8 = @truncate(halPioRead(1, blk + byte_index));
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const en: u8 = @truncate(halPioRead(1, blk + status_bytes + byte_index));
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const active = sts & en;
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if (active == 0) continue;
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var bit: u3 = 0;
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while (true) : (bit += 1) {
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if (active & (@as(u8, 1) << bit) != 0) {
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dispatchGpe(gpe_base + @as(u32, byte_index) * 8 + bit);
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}
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if (bit == 7) break;
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}
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halPioWrite(1, blk + byte_index, active); // write-1-to-clear the serviced bits
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}
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}
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/// Evaluate the `\_GPE._L%02X` or `_E%02X` handler for GPE number `n`, then
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/// publish an event for each device it notified.
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fn dispatchGpe(n: u32) void {
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const gpe_scope = aml.Namespace.resolve(&persistent_namespace, persistent_namespace.root, true, 0, &.{seg4("_GPE")}) orelse return;
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var name: [4]u8 = .{ '_', 'L', 0, 0 };
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writeHex2(name[2..4], n);
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var method = aml.Namespace.childOf(gpe_scope, name);
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if (method == null) {
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name[1] = 'E';
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method = aml.Namespace.childOf(gpe_scope, name);
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}
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const m = method orelse return; // no handler — the status bit was already cleared
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_ = global_interpreter.evaluate(m, &.{}) catch return;
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for (global_interpreter.takeNotifications()) |event| publishNotify(event.node, event.code);
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}
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fn publishNotify(node: *aml.Node, code: u64) void {
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// Map the notified device's _HID to a domain event where we recognize it.
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var hid: [8]u8 = .{0} ** 8;
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if (readHid(node, &global_interpreter)) |h| hid = h;
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const which: power.Event = if (std.mem.eql(u8, hid[0..7], "PNP0C0A")) .battery else if (std.mem.eql(u8, hid[0..7], "ACPI0003")) .ac else if (std.mem.eql(u8, hid[0..7], "PNP0C0D")) .lid else .notify;
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var event = power.EventMessage{ .event = @intFromEnum(which), .code = @truncate(code) };
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event.hid = hid;
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writeLine("power: notify {s} code {d}\n", .{ hid[0..7], code });
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publishEvent(std.mem.asBytes(&event));
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}
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/// Two lowercase hex digits of `n` into `out[0..2]`.
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fn writeHex2(out: []u8, n: u32) void {
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const digits = "0123456789ABCDEF";
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out[0] = digits[(n >> 4) & 0xF];
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out[1] = digits[n & 0xF];
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}
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fn publishButton() void {
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const event = power.EventMessage{ .event = @intFromEnum(power.Event.power_button) };
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publishEvent(std.mem.asBytes(&event));
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}
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fn publishEvent(bytes: []const u8) void {
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for (&subscribers) |*slot| {
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if (slot.*) |handle| {
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if (!runtime.ipc.send(handle, bytes)) slot.* = null;
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}
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}
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}
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fn isSubscriber(task: u32) bool {
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for (&subscribers, 0..) |*slot, si| {
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if (slot.* != null and subscriber_tasks[si] == task) return true;
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}
|
||||
return false;
|
||||
}
|
||||
|
||||
/// Enter S5 (soft off): write SLP_TYP|SLP_EN to the PM1 control register(s).
|
||||
/// Mirrors the kernel's power.zig sleepValue. Only reached from a PID-1
|
||||
/// shutdown request (M21.3).
|
||||
fn enterS5() void {
|
||||
if (!s5_valid or pm1a_cnt == 0) {
|
||||
_ = runtime.system.write("power: S5 unavailable\n");
|
||||
return;
|
||||
}
|
||||
_ = runtime.system.write("power: entering S5\n");
|
||||
halPioWrite(2, pm1a_cnt, (@as(u32, s5_slp_typ_a & 0x7) << 10) | slp_en);
|
||||
if (pm1b_cnt != 0) halPioWrite(2, pm1b_cnt, (@as(u32, s5_slp_typ_b & 0x7) << 10) | slp_en);
|
||||
// If control returns, the write did not take — say so instead of hanging.
|
||||
runtime.system.sleep(500);
|
||||
_ = runtime.system.write("power: S5 write did not take\n");
|
||||
}
|
||||
|
||||
// --- harness callbacks --------------------------------------------------------
|
||||
|
||||
fn onNotification(badge: u64) void {
|
||||
// The only notification the service binds is the SCI (an IRQ badge).
|
||||
_ = badge;
|
||||
onSci();
|
||||
}
|
||||
|
||||
/// The `.power` protocol: subscribe (endpoint as the call's capability),
|
||||
/// shutdown (PID 1 only). Device discovery uses a different endpoint (the
|
||||
/// device manager's), so nothing here handles ChildAdded.
|
||||
fn onMessage(message: []const u8, reply: []u8, sender: u32, capability: ?runtime.ipc.Handle) usize {
|
||||
if (message.len < 1) return 0;
|
||||
switch (message[0]) {
|
||||
@intFromEnum(power.Operation.subscribe) => {
|
||||
var status: i32 = -1;
|
||||
if (capability) |handle| {
|
||||
for (&subscribers, 0..) |*slot, si| {
|
||||
if (slot.* == null) {
|
||||
slot.* = handle;
|
||||
subscriber_tasks[si] = sender;
|
||||
status = 0;
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
const r = power.Reply{ .status = status };
|
||||
@memcpy(reply[0..@sizeOf(power.Reply)], std.mem.asBytes(&r));
|
||||
return @sizeOf(power.Reply);
|
||||
},
|
||||
@intFromEnum(power.Operation.shutdown) => {
|
||||
// Honored only from a power subscriber — init, which has already run
|
||||
// the stop sequence over everything else. The power service is
|
||||
// mechanism (write S5); deciding *when* to shut down and stopping
|
||||
// the rest of the system first is init's policy.
|
||||
const allowed = isSubscriber(sender);
|
||||
const r = power.Reply{ .status = if (allowed) 0 else -1 };
|
||||
@memcpy(reply[0..@sizeOf(power.Reply)], std.mem.asBytes(&r));
|
||||
if (allowed) enterS5();
|
||||
return @sizeOf(power.Reply);
|
||||
},
|
||||
else => return 0,
|
||||
}
|
||||
}
|
||||
|
||||
/// Depth-first walk: register + report each present device with a _HID, then
|
||||
|
||||
Reference in New Issue
Block a user