wake application processors to long mode

INIT-SIPI-SIPI plus a self-relocating real-mode trampoline.

src/kernel/arch/x86_64/apic.zig

@@ -44,11 +44,15 @@ const spurious_vector = 47;
 // LAPIC register offsets.
 const reg_spurious = 0x0F0;
 const reg_eoi = 0x0B0;
+const reg_icr_low = 0x300; // interrupt command register, low dword (writing it sends)
+const reg_icr_high = 0x310; // ICR high dword (destination APIC id in bits 24-31)
 const reg_lvt_timer = 0x320;
 const reg_timer_initial = 0x380;
 const reg_timer_current = 0x390;
 const reg_timer_divide = 0x3E0;
 
+const icr_delivery_pending = 1 << 12; // ICR low bit 12: a previous IPI is still in flight
+
 const lvt_masked = 1 << 16;
 const lvt_periodic = 1 << 17;
 const timer_divide_16 = 0x3;
@@ -120,6 +124,39 @@ pub fn init() void {
     write(reg_spurious, 0x100 | spurious_vector); // bit 8 = software enable
 }
 
+/// Software-enable *this* core's Local APIC — the application-processor counterpart
+/// of `init`, minus the one-time PIC remap (the BSP already masked it) and minus
+/// calibration (the timer rate is a shared hardware constant, measured once). Each
+/// core has its own LAPIC at the same MMIO address, so no per-core base is needed.
+pub fn initSecondary() void {
+    const msr = io.rdmsr(ia32_apic_base_msr);
+    io.wrmsr(ia32_apic_base_msr, msr | (1 << 11)); // global enable
+    write(reg_spurious, 0x100 | spurious_vector); // software enable
+}
+
+// --- application-processor wakeup (INIT–SIPI–SIPI) --------------------------
+
+/// Send an INIT IPI to the core with Local APIC id `apic_id` — the first step of
+/// the wake sequence. Blocks until the LAPIC reports the IPI was delivered.
+pub fn sendInit(apic_id: u32) void {
+    write(reg_icr_high, apic_id << 24);
+    write(reg_icr_low, 0x4500); // INIT, physical destination, assert, edge-triggered
+    waitIcrIdle();
+}
+
+/// Send a STARTUP IPI (SIPI) telling the target core to begin executing at physical
+/// address `vector << 12` (in real mode). Per the Intel bring-up protocol this is
+/// sent twice after the INIT; both calls block until delivery completes.
+pub fn sendStartup(apic_id: u32, vector: u8) void {
+    write(reg_icr_high, apic_id << 24);
+    write(reg_icr_low, 0x4600 | @as(u32, vector)); // STARTUP with the page vector
+    waitIcrIdle();
+}
+
+fn waitIcrIdle() void {
+    while (read(reg_icr_low) & icr_delivery_pending != 0) {}
+}
+
 /// The calibration window: we time everything against a 10 ms reference interval.
 const calib_ms = 10;