kernel: the IOMMU backends move behind the architecture boundary

VT-d and AMD-Vi are x86 hardware, but lived in the architecture-neutral
kernel tree and leaked further: the core's public Kind enum named both
vendors, and the ACPI parser read the VT-d version/capability registers
(raw volatile MMIO inside table discovery). Now the vendor backends
live in architecture/x86_64/ behind architecture.iommu — the core hands
over the discovery facts plus an injected environment (frame allocation
+ the log sink, the same pattern enablePaging uses) and receives the
hardware vtable back, so the backends never import kernel internals and
an ARM port supplies its SMMU with no core change. Discovery keeps
table facts only; the live-unit register check moved into VT-d detect
(version reading zero now stays fail-open). The unused kindOf() is
gone. Log shapes the harness pins (iommu online, DANOS-IOMMU-FAULT)
are unchanged; all five IOMMU QEMU cases pass.

system/kernel/acpi.zig

@@ -106,12 +106,6 @@ pub const PlatformInformation = struct {
     /// INCLUDE_PCI_ALL (the catch-all unit; falls back to the first), or the AMD-Vi
     /// IOMMU's control-register base from the first IVHD.
     iommu_base: u64 = 0,
-    /// The unit's Version register (offset 0x00) — its low byte is major.minor;
-    /// reading it back nonzero confirms a real, mappable VT-d unit.
-    iommu_version: u32 = 0,
-    /// The unit's Capability register (offset 0x08): supported address widths, number
-    /// of domains, etc. Consumed by the IOMMU core when it enables translation.
-    iommu_capabilities: u64 = 0,
     /// Whether the selected unit carries INCLUDE_PCI_ALL. False means every unit is
     /// device-scoped (unusual) — the core still enables on the selected unit but
     /// devices outside its scope remain untranslated.
@@ -502,7 +496,7 @@ fn handleTable(device_tree: *DeviceTree, hal: Hal, sdt_physical: u64) !void {
     } else if (std.mem.eql(u8, &sig, &SPCR)) {
         parseSpcr(header);
     } else if (std.mem.eql(u8, &sig, &DMAR)) {
-        parseDmar(hal, header);
+        parseDmar(header);
     } else if (std.mem.eql(u8, &sig, &IVRS)) {
         parseIvrs(header);
     } else if (std.mem.eql(u8, &sig, &SSDT)) {
@@ -822,7 +816,7 @@ const scope_path_offset = 6;
 /// and records single-path endpoint RMRRs for the IOMMU core to pre-map before it
 /// enables translation. Multi-hop RMRR scopes are skipped loudly: better a named gap
 /// than a silent one.
-fn parseDmar(hal: Hal, header: *const SystemDescriptorTableHeader) void {
+fn parseDmar(header: *const SystemDescriptorTableHeader) void {
     const base: [*]align(1) const u8 = @ptrCast(header);
     const total: usize = header.length;
 
@@ -840,13 +834,14 @@ fn parseDmar(hal: Hal, header: *const SystemDescriptorTableHeader) void {
                 const replace = !platform_information.iommu_present or
                     (include_all and !platform_information.iommu_include_all);
                 if (replace) {
+                    // Table facts only: the unit's registers are the IOMMU
+                    // backend's business (it maps and validates them at
+                    // detect) — discovery records where they live, never
+                    // reads them.
                     if (platform_information.iommu_present) platform_information.iommu_extra_units += 1;
-                    const regs = hal.mapMmio(register_base, abi.page_size, true);
                     platform_information.iommu_present = true;
                     platform_information.iommu_base = register_base;
                     platform_information.iommu_include_all = include_all;
-                    platform_information.iommu_version = @as(*const volatile u32, @ptrFromInt(regs + 0x00)).*;
-                    platform_information.iommu_capabilities = @as(*const volatile u64, @ptrFromInt(regs + 0x08)).*;
                 } else {
                     platform_information.iommu_extra_units += 1;
                 }