Commit Graph

153 Commits

Author SHA1 Message Date
Daniel Samson 75bc429aa1
M2 step 1-2: loader builds bootstrap tables + CR3 handoff
Add the higher-half layout constants (physToVirt/virtToPhys, physmap
and kernel bases) to the danos handoff module, and KernelSegment.phys
so the loader records where it actually placed each segment.

The loader now builds its own page tables before ExitBootServices —
identity + a physmap of low RAM (2 MiB pages) plus 4 KiB mappings for
any higher-half kernel segment — and switches CR3, then calls the entry
with boot_info in RDI, interrupts off. The kernel still links and runs
low (identity), oblivious; this proves the CR3 dance in isolation.
Suite 27/27.

Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
2026-07-08 22:28:43 +01:00
Daniel Samson 91aff2bc4a
pin the kernel to LLVM+LLD
The self-hosted linker ignores parts of linker.ld (PHDRS, /DISCARD/,
section order). The higher-half move needs the script authoritative.
Suite 27/27 on the LLD build.

Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
2026-07-08 22:17:02 +01:00
Daniel Samson 546dd44a2a
isolation M1: ring 3 + a real /sbin/init, end to end
Ring 3 works: user GDT descriptors (sysret-ready layout), TSS.rsp0,
U/S-bit user mappings (W^X preserved), an int 0x80 syscall gate with a
mutable trap frame, and a setjmp-style enter/exit path. /sbin/init is a
real freestanding Zig binary built from sbin/, shipped on the ESP,
loaded by the bootloader (BootInfo.init_base/len), validated and mapped
by an in-kernel user-ELF loader, and run at CPL 3 — syscalls: exit,
ping, write. Tests: user, user-pf (U/S isolation proof, error code
0x5), init. Suite 27/27.

Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
2026-07-08 22:15:07 +01:00
Daniel Samson 7501bd1703
gather kernel tunables into config.zig
max_cpus, max_tasks, kernel/IST stack sizes, and timer_hz move from scattered constants into one config module. root.zig goes back to being just the boot contract. Values unchanged; any can become a -D build option later.
2026-07-08 16:26:36 +01:00
Daniel Samson 1b47de5058
allocate AP kernel/IST stacks at bring-up, not statically
Hoist max_cpus into danos (root.zig), raise it to 128, and stop reserving a static [max_cpus][16 KiB] IST array. Only the BSP's IST stack is static (needed before the allocator); each AP's is heap-allocated when it comes online. Shrinks the kernel from ~1.1 MB to ~139 KiB in ReleaseSmall.
2026-07-08 16:04:18 +01:00
Daniel Samson 26ac97df31
test fault-on-AP and affinity; report the faulting core
fault-ap-df pins a #DF to an AP (its own IST must catch it); affinity checks a pinned task never migrates. onException now names the core, so an AP fault is attributed and shown contained. Both teeth-checked.
2026-07-08 14:45:28 +01:00
Daniel Samson 37f72a4df8
add thread affinity: pin a task to a core
spawnOn(entry, priority, cpu) routes to a per-core pinned queue, merged with the global queue at O(1) selection. Falls back to unpinned for an offline/invalid core.
2026-07-08 14:45:28 +01:00
Daniel Samson f02259cae0
close audited test gaps: discovery, W^X, power
Add a discovery case (asserts stable ACPI/MADT/FADT/AML facts) and a wx case (audits R+X code vs NX data/rodata/heap/stack via arch.pageExecutable). Wire the existing poweroff/reboot cases into the harness. Suite: 18 -> 22.
2026-07-08 14:17:54 +01:00
Daniel Samson 5940864958
test the trampoline is inert (zeroed + NX) when dormant
Adds paging.isExecutable and arch.trampolinePage; the smp case now asserts the frame is zeroed and non-executable after bring-up. Teeth-checked against a no-op disarm.
2026-07-08 13:46:53 +01:00
Daniel Samson 91f2cfa17b
add smp-retry test for the AP wake retry path
Test hook forces the first wake to fail; the case asserts every core still comes online. Verified it fails when retry is disabled.
2026-07-08 13:41:14 +01:00
Daniel Samson debe815a5c
keep the AP trampoline inert between wakes, and retry failed cores
Arm the low frame (copy blob, make executable) only while a core climbs, then zero it and restore RW+NX; the frame stays reserved so cores can be re-woken. startSecondary is one re-runnable attempt; boot retries a non-responding core 3x. Validated the retry path by forcing a first-attempt failure.
2026-07-08 13:32:34 +01:00
Daniel Samson dba3939a0f
add an SMP lock-stress test case
Four pairs push 400k sequenced messages through small channels; checks FIFO order and cross-core execution. Verified to fail with the lock disabled.
2026-07-08 12:45:02 +01:00
Daniel Samson 43afe6bf2e
schedule tasks across all cores
Per-core GDT/TSS and AP scheduler entry; fix AP SSE + single_threaded.
2026-07-08 12:35:30 +01:00
Daniel Samson ed7f542006
wake application processors to long mode
INIT-SIPI-SIPI plus a self-relocating real-mode trampoline.
2026-07-08 12:35:30 +01:00
Daniel Samson 36c29d2d6d
move the running task into per-CPU state
PerCpu.current via the GS base; ready queues stay global.
2026-07-08 12:35:30 +01:00
Daniel Samson 941ab091db
add a big kernel lock for SMP
Guards the scheduler and IPC; held across the context switch.
2026-07-08 12:35:30 +01:00
Daniel Samson cf7c6df41c
enumerate usable CPU cores from the MADT
Keep each Local APIC's id and expose platform.cpus().
2026-07-08 12:35:30 +01:00
Daniel Samson 26d2f5259c
document the multi-sink logging model 2026-07-08 10:41:47 +01:00
Daniel Samson cb63d2e31b
add multi-sink diagnostic log; make framebuffer optional 2026-07-08 10:40:22 +01:00
Daniel Samson 7d3417fe86
refactor kernel to use device platform discovery 2026-07-08 10:06:46 +01:00
Daniel Samson 2ee898a91e
add device platform module with ACPI support 2026-07-08 09:23:41 +01:00
Daniel Samson 53a33a7332
fix debug typos 2026-07-05 19:07:22 +01:00
Daniel Samson 3f17ebf175
rename sched to scheduler 2026-07-05 19:03:07 +01:00
Daniel Samson 6f6ccc8bc9 moving kernel code to kernel/ 2026-07-05 10:19:11 +01:00
Daniel Samson 7c3cffb337 moving efi code to boot 2026-07-05 10:01:01 +01:00
Daniel Samson ae1552414d printing debug messages to serial only 2026-07-05 09:48:06 +01:00
Daniel Samson 6cd6669a8d Add RAM and VRAM footprint 2026-07-05 09:10:59 +01:00
Daniel Samson d055de7141 documenting things to research 2026-07-03 21:40:59 +01:00
Daniel Samson a6de418e42 documenting smp and scheduling to research 2026-07-03 21:24:44 +01:00
Daniel Samson f9f0511ac2 documenting research for arm and device discovery 2026-07-03 20:22:48 +01:00
Daniel Samson 99d6bf5ce3 renaming run-efi to run-x86-64 2026-07-03 19:45:44 +01:00
Daniel Samson 21b9691486 reclaiming uefi memory 2026-07-03 19:31:32 +01:00
Daniel Samson 50f3610768
Update build to run qemu on MacOS 2026-07-03 16:43:00 +01:00
Daniel Samson 31bf86af56 IPC 2026-07-03 15:09:16 +01:00
Daniel Samson df774691c8 Fixed-priority preemptive scheduler 2026-07-03 14:30:33 +01:00
Daniel Samson e80043b611 Calibrated timer / clock 2026-07-03 14:17:00 +01:00
Daniel Samson 9a834c91ff Pin zig version to 0.16 LTS 2026-07-03 13:49:47 +01:00
Daniel Samson 269729f2f2 Built heap allocation 2026-07-03 13:41:55 +01:00
Daniel Samson 20b4661ff3 Hardened paging into a real VMM 2026-07-03 13:29:34 +01:00
Daniel Samson d910e6261a Documenting sysv 2026-07-03 13:06:43 +01:00
Daniel Samson 56219b4050 Documenting sysv 2026-07-03 13:06:27 +01:00
Daniel Samson 5ea521d054 Built device interrupts 2026-07-03 12:57:40 +01:00
Daniel Samson c8e89e8115 Cross-architecture test suite 2026-07-03 12:39:26 +01:00
Daniel Samson 9cf135302d Built paging / the kernel's own page tables (with a TSS+IST) 2026-07-03 12:23:55 +01:00
Daniel Samson 0cc71ec8aa Built GDT + IDT + exception handlers 2026-07-03 12:05:41 +01:00
Daniel Samson 6312e84262 added physical memory manager 2026-07-03 11:43:14 +01:00
Daniel Samson cb2f49cb48 added physical memory manager 2026-07-03 11:24:26 +01:00
Daniel Samson 628c4f6d57 Move to multi arch support and added memory map 2026-07-03 11:11:19 +01:00
Daniel Samson c2435760c4 Add README file in docs 2026-07-03 10:31:08 +01:00
Daniel Samson 6a08081bfe selecting the displays native resolution 2026-07-03 10:07:51 +01:00