Commit Graph

4 Commits

Author SHA1 Message Date
Daniel Samson bb7597ea0b
M2 step 5: drop the low half — a true higher-half kernel
paging.init now maps only the physmap, the framebuffer/LAPIC windows,
and the kernel's own segments; the entire low canonical half is left to
user space. Every higher-half PML4 entry is pre-created so a per-process
address space can share the kernel half by copying PML4[256..512), with
an assert against late top-half entries and a 4 GiB guard on
pre-switch table frames. The AP trampoline's low identity page is now
created transiently by arm() and unmapped by disarm(); startAp asserts
the page-table root is 32-bit addressable. Docs (paging.md) updated.
Suite 27/27; 4-core normal boot reaches /sbin/init.

Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
2026-07-08 22:54:52 +01:00
Daniel Samson 6f6ccc8bc9 moving kernel code to kernel/ 2026-07-05 10:19:11 +01:00
Daniel Samson 20b4661ff3 Hardened paging into a real VMM 2026-07-03 13:29:34 +01:00
Daniel Samson 9cf135302d Built paging / the kernel's own page tables (with a TSS+IST) 2026-07-03 12:23:55 +01:00