Daniel Samson
125a3b4993
An HCD programs a bus-master engine: it needs a descriptor ring that is physically contiguous, at a physical address it knows, uncacheable, and pinned. mmap gives none of those. Add dma_alloc(len, flags) -> vaddr (rax), paddr (rdx) and dma_free(vaddr, len): grant contiguous, zeroed, pinned, strong-uncacheable memory in a per-process DMA arena (PML4[228]) and hand back both addresses. Pieces: pmm.allocContiguous(count, max_phys) finds a run of contiguous free frames below a cap (dma_below_4g for 32-bit engines); mapUserDmaInto maps them uncacheable (PCD|PWT) but WITHOUT device_grant, so unlike an MMIO grant these frames are real RAM and freeSubtree returns them on teardown — a driver that dies leaks nothing. dma_free is bounded to the DMA arena so it can never unmap the caller's stack/heap/MMIO. dma_write_combining is accepted but falls back to coherent (WC needs PAT programming). Runtime: runtime.dma.alloc/free (a two-return-value stub, like replyWait). New `dma` kernel test drives the mechanism directly — contiguity, the below-4G cap, coherent mapping, and reclaim-on-teardown (no leak). The thin syscall wrappers follow the tested mmap/mmio_map shape and land their first real use with the first DMA driver. Suite 38/38 plus host tests.
49 lines
2.0 KiB
Zig
49 lines
2.0 KiB
Zig
//! User-space DMA memory: `dma_alloc` / `dma_free`. A driver that programs a
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//! bus-mastering engine needs a descriptor ring the device can read — memory that is
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//! physically contiguous, at a physical address the driver knows, uncacheable, and
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//! pinned. `mmap` gives none of those; this does. Pair it with the barriers in
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//! `/lib/mmio` (fill the ring, `wmb()`, ring the doorbell). See docs/driver-model.md.
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const abi = @import("abi");
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const sc = @import("system-call.zig");
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/// Allocation flags. `coherent` (uncacheable) is the portable default; the rest are
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/// opt-in for specific hardware — see `abi`.
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pub const coherent: usize = abi.dma_coherent;
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pub const write_combining: usize = abi.dma_write_combining;
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pub const below_4g: usize = abi.dma_below_4g;
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/// A DMA allocation: the `virtual` address the CPU touches, and the `physical` address
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/// to program into the device's descriptor-ring / base registers.
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pub const Region = struct {
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virtual: usize,
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physical: usize,
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};
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inline fn failed(r: usize) bool {
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return r > ~@as(usize, 0) - 4095;
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}
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/// Allocate `len` bytes of DMA-capable memory with `flags` (e.g. `coherent`, or
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/// `coherent | below_4g`). Returns the virtual/physical pair, or null on failure. Two
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/// return values — the virtual address in rax, the physical address in rdx — so it
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/// needs a hand-written stub.
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pub fn alloc(len: usize, flags: usize) ?Region {
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var rax: usize = undefined;
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var rdx: usize = undefined; // out: physical address
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asm volatile ("syscall"
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: [rax] "={rax}" (rax),
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[rdx] "={rdx}" (rdx),
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: [n] "{rax}" (@intFromEnum(abi.SystemCall.dma_alloc)),
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[a0] "{rdi}" (len),
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[a1] "{rsi}" (flags),
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: .{ .rcx = true, .r11 = true, .memory = true });
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if (failed(rax)) return null;
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return .{ .virtual = rax, .physical = rdx };
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}
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/// Release a region from a prior `alloc` (`virtual` and the same `len`).
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pub fn free(virtual: usize, len: usize) void {
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_ = sc.systemCall2(.dma_free, virtual, len);
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}
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