179 lines
10 KiB
Zig
179 lines
10 KiB
Zig
//! pci-cap-test — QEMU fixture for the driver-side PCI library (library/device/pci).
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//! The pci-caps test case boots with an extra `-device e1000e` NIC that no danos driver
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//! claims; this fixture claims it and exercises the whole claimed-function surface
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//! against real (emulated) hardware: header accessors, command bits, the capability
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//! walk, MSI programming (the first driver-side `msi_bind` use), the MSI-X table,
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//! extended capabilities, power state, and — where offered — function-level reset.
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//! Every check prints `pci-cap-test: <check> ok` or `pci-cap-test: FAIL <check>`; the
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//! harness asserts on the final `all checks passed` marker (test/qemu_test.py).
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const std = @import("std");
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const device = @import("driver");
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const ipc = @import("ipc");
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const time = @import("time");
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const logging = @import("logging");
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const mmio = @import("mmio");
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const pci = @import("pci");
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const pci_class = @import("pci-class");
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/// QEMU's e1000e: Intel 82574L.
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const intel_vendor: u16 = 0x8086;
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const e1000e_device: u16 = 0x10D3;
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const ethernet_class: u64 = pci_class.ClassCode.pack(.{
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.base = @intFromEnum(pci_class.BaseClass.network),
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.subclass = @intFromEnum(pci_class.network.SubClass.ethernet),
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.prog_if = 0,
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});
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/// `pci.Function` keeps a pointer to the descriptor, so it must outlive the stack frame
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/// that found it.
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var descriptor: device.DeviceDescriptor = undefined;
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fn writeLine(comptime fmt: []const u8, arguments: anytype) void {
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var line: [128]u8 = undefined;
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_ = logging.write(std.fmt.bufPrint(&line, fmt, arguments) catch return);
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}
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/// Print the check's verdict; the caller returns on false to stop at the first failure.
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fn check(comptime name: []const u8, ok: bool) bool {
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if (ok) {
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_ = logging.write("pci-cap-test: " ++ name ++ " ok\n");
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} else {
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_ = logging.write("pci-cap-test: FAIL " ++ name ++ "\n");
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}
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return ok;
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}
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pub fn main() void {
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// The bus scan runs in another process; poll until the NIC shows up.
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const nic_id: u64 = found: {
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var tries: u32 = 0;
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while (tries < 150) : (tries += 1) {
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var descriptors: [64]device.DeviceDescriptor = undefined;
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const total = device.enumerate(&descriptors);
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for (descriptors[0..@min(total, descriptors.len)]) |*entry| {
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if (entry.class == @intFromEnum(device.DeviceClass.pci_device) and entry.pci_class == ethernet_class) {
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descriptor = entry.*;
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break :found entry.id;
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}
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}
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time.sleepMillis(100);
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}
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_ = logging.write("pci-cap-test: FAIL no ethernet function found\n");
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return;
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};
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writeLine("pci-cap-test: claiming ethernet function (device {d})\n", .{nic_id});
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if (!check("claim", device.claim(nic_id))) return;
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var function = pci.Function.map(nic_id, &descriptor) orelse {
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_ = logging.write("pci-cap-test: FAIL config-space map\n");
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return;
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};
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// Identity: the header accessors against known e1000e values.
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if (!check("vendor/device id", function.vendorId() == intel_vendor and function.deviceId() == e1000e_device)) return;
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if (!check("class code", function.classCode().pack() == ethernet_class)) return;
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if (!check("subsystem ids readable", function.subsystemVendorId() != 0xFFFF and function.subsystemId() != 0xFFFF)) return;
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// Command bits: enable, read back, quiesce, read back, re-enable.
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function.enableMemoryAndBusMaster();
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if (!check("memory+bus-master enable", function.command() & pci_class.command_memory_and_bus_master == pci_class.command_memory_and_bus_master)) return;
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function.disableBusMaster();
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if (!check("bus-master disable", function.command() & pci_class.command_bus_master == 0)) return;
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function.enableMemoryAndBusMaster();
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// The capability walk: e1000e advertises PM, MSI, PCIe, and MSI-X.
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var seen_power = false;
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var seen_msi = false;
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var seen_pci_express = false;
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var seen_msix = false;
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var walk = function.capabilities();
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while (walk.next()) |capability| {
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switch (capability.id) {
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@intFromEnum(pci_class.CapabilityId.power_management) => seen_power = true,
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@intFromEnum(pci_class.CapabilityId.msi) => seen_msi = true,
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@intFromEnum(pci_class.CapabilityId.pci_express) => seen_pci_express = true,
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@intFromEnum(pci_class.CapabilityId.msix) => seen_msix = true,
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else => {},
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}
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}
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if (!check("capability walk", seen_power and seen_msi and seen_pci_express and seen_msix)) return;
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if (!check("findCapability", function.findCapability(.msi) != null and function.findCapability(.pci_express) != null)) return;
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// MSI: bind a vector (the syscall's first driver-side use), program the capability,
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// and read the registers straight back.
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const endpoint = ipc.createIpcEndpoint() orelse {
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_ = logging.write("pci-cap-test: FAIL endpoint creation\n");
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return;
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};
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const message = device.msiBind(nic_id, endpoint) orelse {
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_ = logging.write("pci-cap-test: FAIL msi_bind\n");
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return;
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};
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if (!check("msi_bind address", message.address == 0xFEE0_0000)) return;
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if (!check("programMsi", function.programMsi(message))) return;
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const msi_cap = function.findCapability(.msi).?;
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const msi_control = mmio.readRegister(u16, msi_cap.offset + pci_class.msi.control);
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const msi_data_offset: usize = if (msi_control & pci_class.msi.control_64bit_capable != 0) pci_class.msi.data_64 else pci_class.msi.data_32;
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if (!check("msi registers read back", msi_control & pci_class.msi.control_enable != 0 and
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msi_control & pci_class.msi.control_multiple_message_enable_mask == 0 and
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mmio.readRegister(u32, msi_cap.offset + pci_class.msi.address) == @as(u32, @truncate(message.address)) and
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mmio.readRegister(u16, msi_cap.offset + msi_data_offset) == @as(u16, @truncate(message.data)))) return;
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if (!check("intx disabled with msi", function.command() & pci_class.command_interrupt_disable != 0)) return;
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function.disableMsi();
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if (!check("disableMsi", mmio.readRegister(u16, msi_cap.offset + pci_class.msi.control) & pci_class.msi.control_enable == 0)) return;
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// MSI-X: map the table, program entry 0, exercise the masks. Never enable — this
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// proves the programming surface, not delivery.
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const msix_table = function.msix() orelse {
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_ = logging.write("pci-cap-test: FAIL msix table map\n");
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return;
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};
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writeLine("pci-cap-test: msix table has {d} entries\n", .{msix_table.entry_count});
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if (!check("msix entry count", msix_table.entry_count >= 1)) return;
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if (!check("msix programEntry", msix_table.programEntry(0, message))) return;
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if (!check("msix entry reads back", mmio.readRegister(u32, msix_table.table + pci_class.msix.entry_address) == @as(u32, @truncate(message.address)) and
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mmio.readRegister(u32, msix_table.table + pci_class.msix.entry_data) == message.data and
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mmio.readRegister(u32, msix_table.table + pci_class.msix.entry_vector_control) & pci_class.msix.entry_vector_control_masked != 0)) return;
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if (!check("msix unmask entry", msix_table.unmaskEntry(0) and
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mmio.readRegister(u32, msix_table.table + pci_class.msix.entry_vector_control) & pci_class.msix.entry_vector_control_masked == 0)) return;
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if (!check("msix re-mask entry", msix_table.maskEntry(0) and
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mmio.readRegister(u32, msix_table.table + pci_class.msix.entry_vector_control) & pci_class.msix.entry_vector_control_masked != 0)) return;
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msix_table.setFunctionMask();
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if (!check("msix function mask", mmio.readRegister(u16, msix_table.capability + pci_class.msix.control) & pci_class.msix.control_function_mask != 0)) return;
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msix_table.clearFunctionMask();
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if (!check("msix function unmask", mmio.readRegister(u16, msix_table.capability + pci_class.msix.control) & pci_class.msix.control_function_mask == 0)) return;
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if (!check("msix out-of-range rejected", !msix_table.programEntry(msix_table.entry_count, message))) return;
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// Extended capabilities: the walk must terminate cleanly; the count is informative
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// (don't hard-bind to QEMU's exact extended-capability set).
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var extended_count: u32 = 0;
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var extended = function.extendedCapabilities();
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while (extended.next()) |_| extended_count += 1;
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writeLine("pci-cap-test: {d} extended capabilities\n", .{extended_count});
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if (!check("extended walk terminates", extended_count < 480)) return;
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// Power: QEMU leaves the function in D0; ensurePowerStateD0 must agree and not
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// disturb the PMCSR.
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const power_cap = function.findCapability(.power_management).?;
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const pmcsr_before = mmio.readRegister(u16, power_cap.offset + pci_class.power_management.control_status);
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if (!check("power state is D0", pmcsr_before & pci_class.power_management.control_status_power_state_mask == pci_class.power_management.power_state_d0)) return;
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function.ensurePowerStateD0();
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if (!check("ensurePowerStateD0 is a no-op at D0", mmio.readRegister(u16, power_cap.offset + pci_class.power_management.control_status) == pmcsr_before)) return;
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// Function-level reset, where the device offers it: afterwards the function must be
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// readable with its identity intact, and bring-up must work again.
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const express_cap = function.findCapability(.pci_express).?;
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const device_capabilities = mmio.readRegister(u32, express_cap.offset + pci_class.pci_express.device_capabilities);
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if (device_capabilities & pci_class.pci_express.device_capabilities_flr != 0) {
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if (!check("functionLevelReset", function.functionLevelReset())) return;
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if (!check("identity after flr", function.vendorId() == intel_vendor and function.deviceId() == e1000e_device)) return;
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function.enableMemoryAndBusMaster();
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if (!check("re-enable after flr", function.command() & pci_class.command_memory_and_bus_master == pci_class.command_memory_and_bus_master)) return;
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} else {
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_ = logging.write("pci-cap-test: flr not offered, skipped\n");
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}
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_ = logging.write("pci-cap-test: all checks passed\n");
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}
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