730 lines
28 KiB
Zig
730 lines
28 KiB
Zig
//! x86_64 CPU operations. This is the "architecture" module: the generic kernel imports
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//! it as `@import("architecture")` and never names x86_64 directly, so a second
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//! architecture is added by pointing that module at a different directory in
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//! build.zig — no change to the generic code. Keep everything CPU-specific here
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//! (halt, the descriptor tables, later paging), and nothing generic.
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const boot_handoff = @import("boot-handoff");
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const parameters = @import("parameters");
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const gdt = @import("gdt.zig");
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const tss = @import("tss.zig");
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const idt = @import("idt.zig");
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const paging = @import("paging.zig");
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const serial = @import("serial.zig");
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const apic = @import("apic.zig");
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const ioapic = @import("ioapic.zig");
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const io = @import("io.zig");
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const smp = @import("smp.zig");
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const pcpu = @import("per-cpu.zig");
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/// The saved register/trap frame passed to a fault handler.
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pub const CpuState = idt.CpuState;
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// --- trap-frame accessors ---------------------------------------------------
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// The frame's fields are x86_64 registers; the generic kernel reads it through
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// these accessors so it never names one.
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/// The interrupted/faulting instruction address (RIP here; ELR_EL1 on aarch64,
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/// sepc on riscv64).
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pub fn instructionPointer(state: *const CpuState) u64 {
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return state.rip;
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}
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/// The interrupted stack pointer (RSP here).
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pub fn stackPointer(state: *const CpuState) u64 {
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return state.rsp;
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}
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/// Whether the trap came from user mode (CPL 3 here; EL0 on aarch64, U-mode on
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/// riscv64).
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pub fn fromUser(state: *const CpuState) bool {
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return state.cs & 3 == 3;
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}
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/// The faulting virtual address, if this trap is a page fault (CR2 here;
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/// FAR_EL1 on aarch64, stval on riscv64). Null for any other exception.
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pub fn faultAddress(state: *const CpuState) ?u64 {
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if (state.vector != 14) return null;
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return asm volatile ("mov %%cr2, %[out]"
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: [out] "=r" (-> u64),
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);
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}
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// --- system_call ABI ------------------------------------------------------------
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// The System V-style register convention (number in rax, arguments in
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// rdi/rsi/rdx/r10/r8/r9, result in rax), exposed positionally so the generic
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// dispatcher never names a register.
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/// The system_call number the user program passed.
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pub fn systemCallNumber(state: *const CpuState) u64 {
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return state.rax;
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}
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/// Positional system_call argument `n`.
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pub fn systemCallArg(state: *const CpuState, n: u8) u64 {
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return switch (n) {
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0 => state.rdi,
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1 => state.rsi,
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2 => state.rdx,
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3 => state.r10,
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4 => state.r8,
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5 => state.r9,
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else => 0,
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};
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}
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/// Write the system_call's return value into the frame — the entry paths restore
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/// user registers from it.
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pub fn setSystemCallResult(state: *CpuState, value: u64) void {
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state.rax = value;
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}
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/// Write a *second* system_call return value (rdx here — restored by both the
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/// system_call/sysret and int-0x80 entry paths; unlike rcx/r11 it is not consumed by
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/// sysretq). Used by IPC_ReplyWait to hand back the sender's badge alongside the
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/// message length in rax.
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pub fn setSystemCallResult2(state: *CpuState, value: u64) void {
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state.rdx = value;
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}
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/// Write a *third* system_call return value (r8 here). r8 is an input argument
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/// register (arg #4), but the syscall/int-0x80 stubs push and pop it around the
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/// dispatch, so a value written into the frame is restored to the user on return.
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/// Used by the IPC cap-passing calls to hand back the received capability handle.
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pub fn setSystemCallResult3(state: *CpuState, value: u64) void {
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state.r8 = value;
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}
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/// Bring up the serial port (the kernel's machine-readable log). No dependencies,
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/// so it can be the very first thing called.
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pub fn serialInit() void {
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serial.init();
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}
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/// Write bytes to the serial port.
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pub fn serialWrite(bytes: []const u8) void {
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serial.write(bytes);
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}
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/// Whether a working UART was detected (loopback probe). When false the serial
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/// sink is silently inert — a dead legacy COM1 costs nothing per byte.
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pub fn serialPresent() bool {
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return serial.present();
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}
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/// Emit a one-byte progress checkpoint to whatever hardware debug sink the
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/// platform has — here the POST diagnostic port (0x80), which a POST card or BMC
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/// displays. The last-resort progress signal when there's no text output at all.
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/// Writing 0x80 is universally safe (it's the legacy I/O-delay port).
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pub fn checkpoint(code: u8) void {
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io.outb(0x80, code);
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}
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/// Whether a Bochs/QEMU-style debug console is on port 0xE9 (it returns 0xE9 when
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/// read). On real hardware the port reads back 0xFF, so this stays false — a safe
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/// probe before we write to it.
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pub fn debugconPresent() bool {
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return io.inb(0xE9) == 0xE9;
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}
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/// Output sink: write bytes to the 0xE9 debug console (see `debugconPresent`).
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pub fn debugconWrite(bytes: []const u8) void {
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for (bytes) |b| io.outb(0xE9, b);
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}
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/// Set up the CPU's descriptor tables: our own GDT, the TSS (with an interrupt
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/// stack for double faults), then the IDT with exception handlers. After this a
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/// CPU fault is reported instead of triple-faulting. Install the fault handler
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/// (setFaultHandler) first so early faults are caught.
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pub fn init() void {
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gdt.init();
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tss.init();
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idt.init();
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pcpu.initSystemCall();
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}
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/// Build the kernel's own page tables (with real permissions) and switch onto
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/// them. Needs the frame allocator and the boot info (for the memory map and the
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/// kernel's segment layout). Call once the frame allocator is up.
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pub fn enablePaging(allocFrame: *const fn () ?u64, freeFrame: *const fn (u64) void, boot_information: *const boot_handoff.BootInformation) void {
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paging.init(allocFrame, freeFrame, boot_information);
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}
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/// Create a new address space (returns the physical address of its root table —
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/// the PML4 here — or null). Shares the kernel's higher half; the user (low)
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/// half starts empty.
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pub fn createAddressSpace() ?u64 {
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return paging.createAddressSpace();
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}
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/// Free an address space and everything mapped in its user half. Caller must not
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/// be running on it.
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pub fn destroyAddressSpace(root: u64) void {
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paging.destroyAddressSpace(root);
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}
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/// Map a user page into address space `root` (W^X is the caller's contract).
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pub fn mapUserPageInto(root: u64, virtual: u64, physical: u64, writable: bool, executable: bool) void {
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paging.mapUserInto(root, virtual, physical, writable, executable);
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}
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/// Map a device MMIO window into address space `root`: RW+NX, and marked so teardown
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/// won't free the MMIO frames as RAM. `write_combining` picks the cache type —
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/// false = strong-uncacheable (registers), true = write-combining (a framebuffer).
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/// For IO passthrough.
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pub fn mapUserDeviceInto(root: u64, virtual: u64, physical: u64, len: u64, write_combining: bool) void {
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paging.mapUserDeviceInto(root, virtual, physical, len, write_combining);
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}
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/// Is the user leaf mapping `virtual` in address space `root` write-combining? Null if
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/// unmapped. For tests verifying the framebuffer map's cache type.
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pub fn userLeafIsWriteCombining(root: u64, virtual: u64) ?bool {
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return paging.leafIsWriteCombining(root, virtual);
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}
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/// Map coherent DMA RAM into address space `root`: strong-uncacheable, RW+NX, but
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/// reclaimed on teardown (real RAM, not MMIO). For dma_alloc.
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pub fn mapUserDmaInto(root: u64, virtual: u64, physical: u64, len: u64) void {
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paging.mapUserDmaInto(root, virtual, physical, len);
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}
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/// Map a page into the kernel address space (non-executable). For the heap, etc.
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pub fn mapPage(virtual: u64, physical: u64, writable: bool) void {
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paging.map(virtual, physical, writable);
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}
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/// Map a device MMIO range and return the virtual address to reach it at. This
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/// is the device layer's `Hal.mapMmio` — it hands back a physmap pointer and
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/// never exposes how the mapping is placed.
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pub fn mapMmio(physical: u64, len: u64, writable: bool) u64 {
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return paging.mapMmio(physical, len, writable);
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}
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/// The kernel's page-table root (physical), shared into every address space.
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pub fn kernelPageTable() u64 {
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return paging.kernelPml4();
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}
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/// Switch the active address space (load CR3 with a physical root table).
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pub fn loadPageTable(root: u64) void {
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paging.loadCr3(root);
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}
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/// The physical root of the currently active page tables (CR3 here; TTBR0/satp
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/// elsewhere).
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pub fn activePageTable() u64 {
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return asm volatile ("mov %%cr3, %[out]"
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: [out] "=r" (-> u64),
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);
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}
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/// Set core `cpu`'s kernel stack pointer for ring-3 -> ring-0 transitions:
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/// TSS.rsp0 (for interrupts/exceptions, which switch stacks in hardware) and the
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/// per-CPU `kernel_rsp` (for the system_call stub, which switches by hand). Updated
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/// by the scheduler when it switches to a user task.
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pub fn setKernelStack(cpu: usize, top: usize) void {
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tss.rsp0Ptr(cpu).* = top;
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pcpu.setKernelRsp(cpu, top);
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}
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/// Remove a kernel mapping.
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pub fn unmapPage(virtual: u64) void {
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paging.unmap(virtual);
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}
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/// Remove a page mapping from address space `root` (for munmap of user pages).
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/// Clears the leaf entry only; freeing the underlying frame is the caller's job.
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pub fn unmapUserPageInto(root: u64, virtual: u64) void {
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paging.unmapInto(root, virtual);
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}
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/// Resolve `virtual` to its physical address in the address space rooted at `root`
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/// (any address space, not just the live one), or null if unmapped. Used to find
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/// the frame behind a user page for munmap, and for cross-address-space copies.
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pub fn translate(root: u64, virtual: u64) ?u64 {
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return paging.translateIn(root, virtual);
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}
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/// Map a page accessible from ring 3 (U/S bit at every level). The caller keeps
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/// W^X: code read-only + executable, data writable + no-execute.
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pub fn mapUserPage(virtual: u64, physical: u64, writable: bool, executable: bool) void {
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paging.mapUser(virtual, physical, writable, executable);
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}
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// --- ring 3 entry/exit -----------------------------------------------------
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/// Drop to ring 3 at `rip` on `rsp` (defined in isr.s). Saves the kernel context,
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/// publishes the kernel stack pointer through `rsp0_slot` (this core's TSS.rsp0,
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/// so ring-3 interrupts land on a good stack), builds an iretq frame with the
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/// user selectors, and iretq's. "Returns" only when the user program triggers
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/// the exit path (user_exit_to_kernel).
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extern fn enter_user(rip: u64, rsp: u64, rsp0_slot: *align(4) u64) callconv(.c) void;
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/// Abandon the in-flight ring-3 trap context and resume the kernel as if
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/// `enter_user` had returned (defined in isr.s). Called by the exit system_call.
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extern fn user_exit_to_kernel() callconv(.c) noreturn;
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/// Run user code at `entry` with stack `stack_top` on this core (`cpu` = the
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/// caller's CPU index; the architecture layer can't ask the scheduler). Returns after the
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/// user program exits via system_call. Interrupts are disabled on return (the exit
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/// arrives through an interrupt gate) — the caller re-enables.
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pub fn enterUser(cpu: usize, entry: u64, stack_top: u64) void {
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enter_user(entry, stack_top, tss.rsp0Ptr(cpu));
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}
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/// Never returns to the user program: unwind to the kernel context that called
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/// `enterUser`. For the exit system_call's handler.
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pub fn userExit() noreturn {
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user_exit_to_kernel();
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}
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/// Register the handler for the user system_call gate (int 0x80, vector 128). The
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/// handler may write the trap frame (see `setSystemCallResult`).
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pub fn setSystemCallHandler(handler: *const fn (*CpuState) void) void {
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idt.setSystemCallHandler(handler);
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}
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/// Publish core `cpu`'s scheduler pointer via its per-CPU block (GS base). Each
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/// core calls this once, after its GDT is in place (a GS *selector* reload would
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/// clobber the base). See percpu.zig for the swapgs discipline.
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pub fn setCpuLocal(cpu: usize, ptr: usize) void {
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pcpu.setLocal(cpu, ptr);
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}
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/// This core's scheduler pointer (via the GS base) — a per-core register, so each
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/// core sees its own without locking. Valid in any ring-0 context.
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pub fn cpuLocal() usize {
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return pcpu.scheduler();
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}
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// --- SMP: application-processor bring-up ----------------------------------
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/// Record the low (<1 MiB) frame reserved for the AP trampoline. Run once at boot.
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/// The frame stays inert (zeroed, non-executable) between wakes and is armed only
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/// while a core is climbing — so a core can be (re)woken at any time (retry, or a
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/// future power manager) without leaving an executable page resident. See smp.zig.
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pub fn setTrampolinePage(physical: u64) void {
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smp.setTrampolinePage(physical);
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}
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/// Wake the core with hardware id `hw_id` (its Local APIC id here; MPIDR on
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/// aarch64, hart id on riscv64) as dense CPU `index`, giving it `stack_top` and
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/// its per-CPU pointer `percpu`; it adopts the kernel page tables. Returns false
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/// if it doesn't come online within the timeout. Blocks until the core reports in.
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pub fn startSecondary(hw_id: u32, stack_top: usize, percpu: usize, index: usize) bool {
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// The AP adopts the kernel page tables explicitly — never the caller's live
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// CR3, which a future re-wake from a core running a process would make a
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// process address space.
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return smp.startAp(hw_id, stack_top, percpu, index, paging.kernelPml4());
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}
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/// Register the generic entry a woken AP jumps to once its architecture state is up (its own
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/// descriptor tables, LAPIC, and timer). The kernel passes its scheduler entry here.
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pub fn setSecondaryEntry(entry: *const fn () callconv(.c) noreturn) void {
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smp.setSecondaryEntry(entry);
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}
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/// Bytes the kernel should allocate for a secondary core's dedicated fault stack
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/// (the IST double-fault stack here), and where to record its top before waking
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/// the core. The stack is heap-allocated per online core (the boot CPU's is
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/// static — it's needed before the allocator exists). See tss.zig.
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pub const fault_stack_size = tss.ist_stack_size;
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pub fn setFaultStack(cpu: usize, top: usize) void {
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tss.setApIstStack(cpu, top);
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}
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/// Test hook: force the next `n` AP wake attempts to fail, so the retry path can be
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/// exercised deterministically (see the smp-retry test). No effect when `n` is 0.
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pub fn testFailNextWakes(n: u32) void {
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smp.testFailNextWakes(n);
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}
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/// The reserved AP-trampoline frame (0 if none). For tests that check it's inert.
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pub fn trampolinePage() u64 {
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return smp.trampolinePage();
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}
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/// Whether the page at `virtual` is currently mapped executable (present, NX clear).
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pub fn pageExecutable(virtual: u64) bool {
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return paging.isExecutable(virtual);
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}
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/// Kernel tick rate (the scheduler's time quantum), from configuration.
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pub const timer_hz = parameters.timer_hz;
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/// The ACPI PM timer, as a calibration reference (re-exported for the configuration).
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pub const PmTimer = apic.PmTimer;
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/// A MADT interrupt-source override (re-exported for the configuration).
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pub const IsoEntry = ioapic.IsoEntry;
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/// Discovered platform facts the architecture layer needs so it makes no legacy
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/// assumptions — sourced from the device tree + ACPI, passed in by the kernel.
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pub const PlatformConfiguration = struct {
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/// Whether the legacy 8259 PIC is present (skip programming it if not).
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pic_present: bool = true,
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/// HPET MMIO base (0 = none) — a calibration reference for the timer.
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hpet_base: u64 = 0,
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/// The ACPI PM timer, another calibration reference.
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pm_timer: ?PmTimer = null,
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/// I/O APIC MMIO base + its first global system interrupt (0 = none).
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ioapic_base: u64 = 0,
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ioapic_gsi_base: u32 = 0,
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/// MADT ISA-IRQ overrides, for I/O APIC routing.
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overrides: []const IsoEntry = &.{},
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};
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/// Apply the discovered platform configuration. Must run before `startTimer` (the timer
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/// calibration reads `hpet_base`/`pm_timer`) and before any interrupt routing.
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/// Maps + masks the I/O APIC immediately.
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pub fn configurePlatform(configuration: PlatformConfiguration) void {
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apic.configure(configuration.pic_present, configuration.hpet_base, configuration.pm_timer);
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ioapic.configure(configuration.ioapic_base, configuration.ioapic_gsi_base, configuration.overrides);
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ioapic.init();
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}
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/// Point the serial console at the UART ACPI's SPCR table named (MMIO or I/O port).
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pub fn serialReconfigure(is_mmio: bool, address: u64) void {
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serial.reconfigure(is_mmio, address);
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}
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/// The reference clock the timer was calibrated against ("cpuid"/"hpet"/…).
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pub fn timerCalibrationSource() []const u8 {
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return apic.calibrationSource();
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}
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/// External-interrupt-router diagnostics, for boot logging / verification (the
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/// I/O APIC's redirection entries here; a GIC distributor or PLIC elsewhere).
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pub fn irqRouteCount() u32 {
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return ioapic.entryCount();
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}
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pub fn irqRouteRaw(n: u32) u32 {
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return ioapic.entryLow(n);
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}
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// --- device-IRQ plumbing, for system/kernel/irq.zig -----------------------------
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//
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// The generic IRQ layer speaks GSIs and vectors; everything below hides the fact
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// that on x86_64 those mean "I/O APIC redirection entry" and "IDT gate". The
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// vector window is bounded by the stubs isr.s actually emits: `gate_count` = 48,
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// vector 32 is the LAPIC timer and 47 is the spurious vector, leaving 33..46.
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pub const irq_vector_base: u8 = 33;
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pub const irq_vector_count: u8 = 14; // 33..46 inclusive
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/// True if `gsi` is one this machine's interrupt router can deliver.
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pub fn irqOwnsGsi(gsi: u32) bool {
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return ioapic.ownsGsi(gsi);
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}
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/// Install `handler` on `vector` (an absolute IDT gate index).
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pub fn irqSetHandler(vector: u8, handler: *const fn () void) void {
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idt.setHandler(vector, handler);
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}
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/// Route `gsi` to `vector` on *this* core, masked. Unmask with `irqUnmask` once bound.
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pub fn irqRoute(gsi: u32, vector: u8, level: bool, active_low: bool) void {
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ioapic.routeGsi(gsi, vector, apic.localId(), level, active_low);
|
|
}
|
|
|
|
pub fn irqMask(gsi: u32) void {
|
|
ioapic.maskGsi(gsi);
|
|
}
|
|
pub fn irqUnmask(gsi: u32) void {
|
|
ioapic.unmaskGsi(gsi);
|
|
}
|
|
|
|
/// Acknowledge the interrupt currently in service on this core's LAPIC.
|
|
pub fn irqEoi() void {
|
|
apic.eoi();
|
|
}
|
|
|
|
/// Send this core a fixed interrupt at `vector`. Stands in for a device's MSI write
|
|
/// so the MSI vector-routing path can be exercised without MSI-capable hardware.
|
|
pub fn selfIpi(vector: u8) void {
|
|
apic.selfIpi(vector);
|
|
}
|
|
|
|
/// Enable the Local APIC, calibrate its timer against the best available reference
|
|
/// (see apic.calibrate — no longer the PIT by default), and start it firing at
|
|
/// `timer_hz` — the kernel's real-time heartbeat. Interrupts still have to be
|
|
/// unmasked with enableInterrupts() to be delivered. Run `configurePlatform` first.
|
|
pub fn startTimer() void {
|
|
apic.init();
|
|
apic.calibrate();
|
|
idt.setHandler(apic.timer_vector, apic.timerTick);
|
|
apic.initTimer(timer_hz);
|
|
}
|
|
|
|
/// Number of timer ticks since startTimer().
|
|
pub fn ticks() u64 {
|
|
return apic.ticks();
|
|
}
|
|
|
|
// Monotonic high-resolution clock (from the TSC), one function per resolution.
|
|
pub fn nanos() u64 {
|
|
return apic.nanos();
|
|
}
|
|
pub fn micros() u64 {
|
|
return apic.micros();
|
|
}
|
|
pub fn millis() u64 {
|
|
return apic.millis();
|
|
}
|
|
|
|
/// Measured frequency of the tick timer's input clock (the LAPIC timer here), in
|
|
/// Hz, from calibration.
|
|
pub fn timerClockHz() u64 {
|
|
return apic.lapicHz();
|
|
}
|
|
|
|
/// Measured frequency of the monotonic clock's underlying counter (the TSC here;
|
|
/// CNTVCT on aarch64, `time` on riscv64), in Hz.
|
|
pub fn clockHz() u64 {
|
|
return apic.tscHz();
|
|
}
|
|
|
|
// --- real-time clock (CMOS) --------------------------------------------------
|
|
//
|
|
// The battery-backed CMOS clock, read once at boot and thereafter anchored to the
|
|
// monotonic clock (see kernel/wall-clock.zig) — so this is never on a hot path and
|
|
// needs no lock. Wall-clock *seconds* are mechanism the kernel owns (the hardware's
|
|
// value), like the monotonic clock; calendars/timezones are policy layered on top.
|
|
|
|
fn cmosRead(register: u8) u8 {
|
|
io.outb(0x70, register);
|
|
return io.inb(0x71);
|
|
}
|
|
|
|
const RtcFields = struct { second: u8, minute: u8, hour: u8, day: u8, month: u8, year: u8 };
|
|
|
|
fn rtcRaw() RtcFields {
|
|
while (cmosRead(0x0A) & 0x80 != 0) {} // wait out any update in progress (status A bit 7)
|
|
return .{
|
|
.second = cmosRead(0x00),
|
|
.minute = cmosRead(0x02),
|
|
.hour = cmosRead(0x04),
|
|
.day = cmosRead(0x07),
|
|
.month = cmosRead(0x08),
|
|
.year = cmosRead(0x09),
|
|
};
|
|
}
|
|
|
|
fn bcdToBinary(v: u8) u8 {
|
|
return (v & 0x0F) + ((v >> 4) * 10);
|
|
}
|
|
|
|
fn isLeapYear(y: u32) bool {
|
|
return (y % 4 == 0 and y % 100 != 0) or (y % 400 == 0);
|
|
}
|
|
|
|
/// Read the CMOS real-time clock and convert it to Unix epoch seconds (UTC).
|
|
pub fn readRtcUnixSeconds() u64 {
|
|
// Read until two consecutive reads agree, so we never latch a half-updated time.
|
|
var a = rtcRaw();
|
|
while (true) {
|
|
const b = rtcRaw();
|
|
if (a.second == b.second and a.minute == b.minute and a.hour == b.hour and
|
|
a.day == b.day and a.month == b.month and a.year == b.year) break;
|
|
a = b;
|
|
}
|
|
|
|
const status_b = cmosRead(0x0B);
|
|
const binary_mode = status_b & 0x04 != 0; // else BCD
|
|
const hour_24 = status_b & 0x02 != 0; // else 12-hour with a PM bit
|
|
|
|
var second = a.second;
|
|
var minute = a.minute;
|
|
var hour_field = a.hour;
|
|
var day = a.day;
|
|
var month = a.month;
|
|
var year = a.year;
|
|
if (!binary_mode) {
|
|
second = bcdToBinary(second);
|
|
minute = bcdToBinary(minute);
|
|
hour_field = bcdToBinary(hour_field & 0x7F) | (hour_field & 0x80); // preserve the PM bit
|
|
day = bcdToBinary(day);
|
|
month = bcdToBinary(month);
|
|
year = bcdToBinary(year);
|
|
}
|
|
|
|
var hour: u32 = hour_field & 0x7F;
|
|
if (!hour_24) {
|
|
const pm = hour_field & 0x80 != 0;
|
|
hour %= 12; // 12 AM/PM -> 0
|
|
if (pm) hour += 12;
|
|
}
|
|
|
|
// The CMOS year is 0..99; QEMU and modern hardware mean 20xx (there is no
|
|
// reliable century register on QEMU). Treat < 70 as 20xx, else 19xx.
|
|
const full_year: u32 = if (year < 70) 2000 + @as(u32, year) else 1900 + @as(u32, year);
|
|
|
|
var days: u64 = 0;
|
|
var y: u32 = 1970;
|
|
while (y < full_year) : (y += 1) days += if (isLeapYear(y)) 366 else 365;
|
|
const month_lengths = [_]u8{ 31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31 };
|
|
var m: u8 = 1;
|
|
while (m < month) : (m += 1) {
|
|
days += month_lengths[m - 1];
|
|
if (m == 2 and isLeapYear(full_year)) days += 1;
|
|
}
|
|
days += @as(u64, day) - 1;
|
|
|
|
return ((days * 24 + hour) * 60 + minute) * 60 + second;
|
|
}
|
|
|
|
/// Whether the CPU guarantees an **invariant** TSC (CPUID 0x80000007 EDX[8] on
|
|
/// x86; the analogous architectural guarantee elsewhere). When false the TSC is not
|
|
/// used as the clocksource.
|
|
pub fn clockInvariant() bool {
|
|
return apic.tscInvariant();
|
|
}
|
|
|
|
/// Whether the per-core clock counters are synchronized (no backward warp observed
|
|
/// at SMP bring-up). When false the clock falls back off the TSC.
|
|
pub fn clockSynchronized() bool {
|
|
return apic.tscSynced();
|
|
}
|
|
|
|
/// The active monotonic clocksource, for the boot log ("tsc" or "hpet" on x86).
|
|
pub fn clockSourceName() []const u8 {
|
|
return apic.clockSourceName();
|
|
}
|
|
|
|
/// Test hook: force the TSC clocksource on, to exercise the TSC + warp-check path on
|
|
/// a hypervisor that won't advertise an invariant TSC (see apic.forceTscClocksourceForTest).
|
|
pub fn forceTscClocksourceForTest() void {
|
|
apic.forceTscClocksourceForTest();
|
|
}
|
|
|
|
/// How many per-AP TSC warp checks completed (for the tsc-sync test).
|
|
pub fn warpChecksRun() u32 {
|
|
return apic.warpChecksRun();
|
|
}
|
|
|
|
/// Unmask maskable interrupts (`sti`) so device interrupts get delivered.
|
|
pub fn enableInterrupts() void {
|
|
asm volatile ("sti");
|
|
}
|
|
|
|
/// Mask maskable interrupts (`cli`).
|
|
pub fn disableInterrupts() void {
|
|
asm volatile ("cli");
|
|
}
|
|
|
|
/// Disable interrupts and return the previous flags, so a nested critical section
|
|
/// can restore the caller's state rather than blindly re-enabling. Pairs with
|
|
/// restoreInterrupts.
|
|
pub fn saveInterrupts() u64 {
|
|
var flags: u64 = undefined;
|
|
asm volatile (
|
|
\\pushfq
|
|
\\pop %[f]
|
|
\\cli
|
|
: [f] "=r" (flags),
|
|
:
|
|
: .{ .memory = true });
|
|
return flags;
|
|
}
|
|
|
|
/// Re-enable interrupts only if they were enabled when `flags` was captured.
|
|
pub fn restoreInterrupts(flags: u64) void {
|
|
if (flags & 0x200 != 0) asm volatile ("sti" ::: .{ .memory = true }); // bit 9 = IF
|
|
}
|
|
|
|
/// Register a callback the timer interrupt invokes each tick (e.g. the scheduler).
|
|
pub fn setTickHook(hook: *const fn () void) void {
|
|
apic.setTickHook(hook);
|
|
}
|
|
|
|
// --- context switching (for the scheduler) -------------------------------
|
|
|
|
/// Save the current task's registers/stack and resume `new_rsp`; the old stack
|
|
/// pointer is written to `old_rsp`. Defined in isr.s.
|
|
extern fn switch_context(old_rsp: *usize, new_rsp: usize) callconv(.c) void;
|
|
|
|
pub fn switchContext(old_sp: *usize, new_sp: usize) void {
|
|
switch_context(old_sp, new_sp);
|
|
}
|
|
|
|
/// Build the initial stack for a new task so that switching to it lands in
|
|
/// `task_trampoline`, which then calls `entry`. Returns the saved stack pointer.
|
|
/// The layout must match switch_context's push order (callee-saved, then the
|
|
/// return address on top); `entry` is smuggled in via the r15 slot.
|
|
pub fn initTaskStack(stack_top: usize, entry: usize) usize {
|
|
const trampoline = @extern(*const anyopaque, .{ .name = "task_trampoline" });
|
|
var sp = stack_top;
|
|
const push = struct {
|
|
fn f(p: *usize, value: usize) void {
|
|
p.* -= @sizeOf(usize);
|
|
@as(*usize, @ptrFromInt(p.*)).* = value;
|
|
}
|
|
}.f;
|
|
push(&sp, @intFromPtr(trampoline)); // return address for switch_context's `ret`
|
|
push(&sp, 0); // rbx
|
|
push(&sp, 0); // rbp
|
|
push(&sp, 0); // r12
|
|
push(&sp, 0); // r13
|
|
push(&sp, 0); // r14
|
|
push(&sp, entry); // r15 -> task entry, read by task_trampoline
|
|
return sp;
|
|
}
|
|
|
|
/// Drop the current (kernel-context) task to ring 3 at `rip` on `rsp`, never
|
|
/// returning (defined in isr.s). Used by the scheduler's user-task trampoline
|
|
/// once it has switched onto the task and read its entry/stack. Interrupts are
|
|
/// disabled across the swapgs+iretq so no interrupt observes the user GS base in
|
|
/// ring 0; the pushed RFLAGS re-enables them in ring 3.
|
|
extern fn jump_to_user(rip: u64, rsp: u64) callconv(.c) noreturn;
|
|
|
|
pub fn jumpToUser(entry: u64, stack_top: u64) noreturn {
|
|
jump_to_user(entry, stack_top);
|
|
}
|
|
|
|
/// Route CPU exceptions to `handler`, which receives the trap frame and does not
|
|
/// return. Until set, faults just halt the core.
|
|
pub fn setFaultHandler(handler: *const fn (*const CpuState) noreturn) void {
|
|
idt.on_fault = handler;
|
|
}
|
|
|
|
/// A human-readable name for a CPU exception vector.
|
|
pub fn exceptionName(vector: u64) []const u8 {
|
|
return idt.vectorName(vector);
|
|
}
|
|
|
|
/// Read `width` bytes (1/2/4) from an I/O port. The generic device layer drives
|
|
/// ACPI registers through this rather than naming x86 port instructions; on an
|
|
/// MMIO-only architecture this would be implemented differently.
|
|
pub fn pioRead(width: u8, port: u16) u32 {
|
|
return switch (width) {
|
|
1 => io.inb(port),
|
|
2 => io.inw(port),
|
|
4 => io.inl(port),
|
|
else => 0,
|
|
};
|
|
}
|
|
|
|
/// Write `width` bytes (1/2/4) to an I/O port.
|
|
pub fn pioWrite(width: u8, port: u16, value: u32) void {
|
|
switch (width) {
|
|
1 => io.outb(port, @truncate(value)),
|
|
2 => io.outw(port, @truncate(value)),
|
|
4 => io.outl(port, value),
|
|
else => {},
|
|
}
|
|
}
|
|
|
|
/// Park the core forever. `hlt` drops it into a low-power idle until the next
|
|
/// interrupt; the loop re-halts on every wake so the stop is permanent. See
|
|
/// docs/halting.md for the full reasoning.
|
|
pub fn halt() noreturn {
|
|
while (true) asm volatile ("hlt");
|
|
}
|
|
|
|
/// Spin-wait hint (`pause`). Emitted in the body of a spinlock's busy-wait: it
|
|
/// relaxes the core while it polls a contended lock — yielding pipeline resources
|
|
/// to a hyperthread sibling and easing the cache-coherency traffic on the lock
|
|
/// line. Purely a performance/power hint; correct to omit, but kinder on the bus.
|
|
pub fn cpuRelax() void {
|
|
asm volatile ("pause");
|
|
}
|