danos/system/kernel/architecture/x86_64
Daniel Samson 4cb4f2a80f
serial: skip a dead COM1 via a loopback probe (fixes ~57s real-HW boot)
On a legacy-free board COM1 is decoded but has no live UART: its LSR reads 0x00, so the transmit-holding-empty bit never sets and writeByte spun its full 100k-iteration guard on every logged byte (~15ms/byte x ~3.7k bytes to 'initialised' ~= 57s). QEMU always has a working UART, so this only bit real hardware; the boot log survived via log.ramSink.

- probe() loopback-tests the UART in init(); write() is a no-op when absent, so a dead port costs nothing per byte
- guard cut 100k -> 5k (backstop for a live-but-stalled UART only)
- serialPresent() + a boot line making the absent-UART case visible
2026-07-13 21:15:56 +01:00
..
apic.zig Add runtime.time, drop demo drivers, harden TSC timekeeping 2026-07-13 11:56:43 +01:00
cpu.zig serial: skip a dead COM1 via a loopback probe (fixes ~57s real-HW boot) 2026-07-13 21:15:56 +01:00
gdt.zig Re-organize the source tree as a monorepo mirroring the FHS 2026-07-10 12:55:56 +01:00
idt.zig zig fmt 2026-07-12 16:04:58 +01:00
io.zig Re-organize the source tree as a monorepo mirroring the FHS 2026-07-10 12:55:56 +01:00
ioapic.zig Re-organize the source tree as a monorepo mirroring the FHS 2026-07-10 12:55:56 +01:00
isr.s Re-organize the source tree as a monorepo mirroring the FHS 2026-07-10 12:55:56 +01:00
linker.ld Re-organize the source tree as a monorepo mirroring the FHS 2026-07-10 12:55:56 +01:00
paging.zig zig fmt 2026-07-12 16:04:58 +01:00
per-cpu.zig Re-organize the source tree as a monorepo mirroring the FHS 2026-07-10 12:55:56 +01:00
serial.zig serial: skip a dead COM1 via a loopback probe (fixes ~57s real-HW boot) 2026-07-13 21:15:56 +01:00
smp.zig Add runtime.time, drop demo drivers, harden TSC timekeeping 2026-07-13 11:56:43 +01:00
trampoline.s Re-organize the source tree as a monorepo mirroring the FHS 2026-07-10 12:55:56 +01:00
tss.zig Re-organize the source tree as a monorepo mirroring the FHS 2026-07-10 12:55:56 +01:00