262 lines
10 KiB
Zig
262 lines
10 KiB
Zig
//! PCI class-code decoding: turn the (class, subclass, prog-IF) triple a PCI function
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//! reports in its configuration header into human-readable names. Every PCI function
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//! carries a 24-bit class code — base class (config byte 0x0B), subclass (0x0A), and
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//! programming interface (0x09) — that says *what it is* far more precisely than
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//! danos's coarse `DeviceClass`: an ISA bridge, a SATA/AHCI controller, and an xHCI USB
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//! controller are all just `pci_device` by class, and only this triple tells them
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//! apart. Pure reference data (from the PCI spec; see https://wiki.osdev.org/PCI) — no
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//! hardware access — so it is shared by kernel discovery (the device-tree dump) and any
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//! user-space tool (a future lspci, driver matching).
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/// The three bytes of a PCI class code, unpacked from the `0xCCSSPP` value discovery
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/// records in `Device.ids.pci_class` (CC = base class, SS = subclass, PP = prog-IF).
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pub const ClassCode = struct {
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base: u8, // class code (config offset 0x0B)
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subclass: u8, // subclass (0x0A)
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prog_if: u8, // programming interface (0x09)
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pub fn unpack(packed_code: u24) ClassCode {
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return .{
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.base = @intCast((packed_code >> 16) & 0xFF),
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.subclass = @intCast((packed_code >> 8) & 0xFF),
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.prog_if = @intCast(packed_code & 0xFF),
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};
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}
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};
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/// Name of the base class (byte 0x0B), e.g. `0x06` -> "Bridge".
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pub fn className(base: u8) []const u8 {
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return switch (base) {
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0x00 => "Unclassified",
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0x01 => "Mass Storage Controller",
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0x02 => "Network Controller",
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0x03 => "Display Controller",
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0x04 => "Multimedia Controller",
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0x05 => "Memory Controller",
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0x06 => "Bridge",
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0x07 => "Simple Communication Controller",
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0x08 => "Base System Peripheral",
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0x09 => "Input Device Controller",
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0x0A => "Docking Station",
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0x0B => "Processor",
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0x0C => "Serial Bus Controller",
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0x0D => "Wireless Controller",
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0x0E => "Intelligent Controller",
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0x0F => "Satellite Communication Controller",
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0x10 => "Encryption Controller",
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0x11 => "Signal Processing Controller",
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0x12 => "Processing Accelerator",
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0x13 => "Non-Essential Instrumentation",
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0x40 => "Co-Processor",
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0xFF => "Unassigned Class (Vendor specific)",
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else => "Unknown",
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};
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}
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/// Name of the subclass within its base class, e.g. `(0x06, 0x01)` -> "ISA Bridge".
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/// Subclass `0x80` is "Other" by PCI convention; anything unlisted is "Unknown".
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pub fn subclassName(base: u8, subclass: u8) []const u8 {
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return switch (base) {
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0x01 => switch (subclass) {
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0x00 => "SCSI Bus Controller",
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0x01 => "IDE Controller",
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0x02 => "Floppy Disk Controller",
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0x03 => "IPI Bus Controller",
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0x04 => "RAID Controller",
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0x05 => "ATA Controller",
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0x06 => "Serial ATA Controller",
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0x07 => "Serial Attached SCSI Controller",
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0x08 => "Non-Volatile Memory Controller",
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else => defaultSubclass(subclass),
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},
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0x02 => switch (subclass) {
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0x00 => "Ethernet Controller",
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0x01 => "Token Ring Controller",
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0x02 => "FDDI Controller",
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0x03 => "ATM Controller",
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0x04 => "ISDN Controller",
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0x06 => "PICMG 2.14 Multi Computing Controller",
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0x07 => "Infiniband Controller",
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0x08 => "Fabric Controller",
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else => defaultSubclass(subclass),
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},
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0x03 => switch (subclass) {
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0x00 => "VGA Compatible Controller",
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0x01 => "XGA Controller",
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0x02 => "3D Controller (Not VGA-Compatible)",
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else => defaultSubclass(subclass),
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},
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0x04 => switch (subclass) {
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0x00 => "Multimedia Video Controller",
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0x01 => "Multimedia Audio Controller",
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0x02 => "Computer Telephony Device",
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0x03 => "Audio Device",
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else => defaultSubclass(subclass),
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},
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0x05 => switch (subclass) {
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0x00 => "RAM Controller",
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0x01 => "Flash Controller",
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else => defaultSubclass(subclass),
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},
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0x06 => switch (subclass) {
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0x00 => "Host Bridge",
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0x01 => "ISA Bridge",
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0x02 => "EISA Bridge",
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0x03 => "MCA Bridge",
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0x04 => "PCI-to-PCI Bridge",
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0x05 => "PCMCIA Bridge",
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0x06 => "NuBus Bridge",
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0x07 => "CardBus Bridge",
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0x08 => "RACEway Bridge",
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0x09 => "PCI-to-PCI Bridge (Semi-Transparent)",
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0x0A => "InfiniBand-to-PCI Host Bridge",
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else => defaultSubclass(subclass),
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},
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0x07 => switch (subclass) {
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0x00 => "Serial Controller",
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0x01 => "Parallel Controller",
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0x02 => "Multiport Serial Controller",
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0x03 => "Modem",
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0x04 => "IEEE 488.1/2 (GPIB) Controller",
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0x05 => "Smart Card Controller",
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else => defaultSubclass(subclass),
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},
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0x08 => switch (subclass) {
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0x00 => "PIC",
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0x01 => "DMA Controller",
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0x02 => "Timer",
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0x03 => "RTC Controller",
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0x04 => "PCI Hot-Plug Controller",
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0x05 => "SD Host Controller",
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0x06 => "IOMMU",
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else => defaultSubclass(subclass),
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},
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0x09 => switch (subclass) {
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0x00 => "Keyboard Controller",
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0x01 => "Digitizer Pen",
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0x02 => "Mouse Controller",
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0x03 => "Scanner Controller",
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0x04 => "Gameport Controller",
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else => defaultSubclass(subclass),
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},
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0x0C => switch (subclass) {
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0x00 => "FireWire (IEEE 1394) Controller",
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0x01 => "ACCESS Bus Controller",
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0x02 => "SSA",
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0x03 => "USB Controller",
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0x04 => "Fibre Channel",
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0x05 => "SMBus Controller",
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0x06 => "InfiniBand Controller",
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0x07 => "IPMI Interface",
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0x08 => "SERCOS Interface (IEC 61491)",
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0x09 => "CANbus Controller",
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else => defaultSubclass(subclass),
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},
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0x0D => switch (subclass) {
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0x00 => "iRDA Compatible Controller",
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0x01 => "Consumer IR Controller",
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0x10 => "RF Controller",
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0x11 => "Bluetooth Controller",
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0x12 => "Broadband Controller",
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0x20 => "Ethernet Controller (802.1a)",
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0x21 => "Ethernet Controller (802.1b)",
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else => defaultSubclass(subclass),
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},
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else => defaultSubclass(subclass),
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};
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}
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fn defaultSubclass(subclass: u8) []const u8 {
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return if (subclass == 0x80) "Other" else "Unknown";
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}
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/// Name of the programming interface, for the subclasses that define standard ones
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/// (IDE modes, SATA/AHCI, NVMe, PCI-bridge decode, UART generation, USB host type).
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/// Returns "" when the prog-IF carries no standard meaning for this class/subclass —
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/// callers just print the hex byte in that case.
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pub fn progIfName(base: u8, subclass: u8, prog_if: u8) []const u8 {
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return switch (base) {
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0x01 => switch (subclass) {
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0x06 => switch (prog_if) { // Serial ATA
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0x00 => "Vendor Specific Interface",
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0x01 => "AHCI 1.0",
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0x02 => "Serial Storage Bus",
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else => "",
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},
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0x08 => switch (prog_if) { // Non-Volatile Memory
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0x01 => "NVMHCI",
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0x02 => "NVM Express",
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else => "",
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},
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else => "",
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},
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0x03 => switch (subclass) {
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0x00 => switch (prog_if) { // VGA Compatible
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0x00 => "VGA Controller",
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0x01 => "8514-Compatible Controller",
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else => "",
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},
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else => "",
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},
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0x06 => switch (subclass) {
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0x04 => switch (prog_if) { // PCI-to-PCI Bridge
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0x00 => "Normal Decode",
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0x01 => "Subtractive Decode",
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else => "",
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},
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else => "",
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},
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0x07 => switch (subclass) {
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0x00 => switch (prog_if) { // Serial Controller
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0x00 => "8250-Compatible (Generic XT)",
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0x01 => "16450-Compatible",
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0x02 => "16550-Compatible",
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0x03 => "16650-Compatible",
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0x04 => "16750-Compatible",
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0x05 => "16850-Compatible",
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0x06 => "16950-Compatible",
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else => "",
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},
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else => "",
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},
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0x0C => switch (subclass) {
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0x03 => switch (prog_if) { // USB Controller
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0x00 => "UHCI Controller",
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0x10 => "OHCI Controller",
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0x20 => "EHCI (USB2) Controller",
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0x30 => "XHCI (USB3) Controller",
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0x80 => "Unspecified",
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0xFE => "USB Device (not a host controller)",
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else => "",
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},
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else => "",
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},
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else => "",
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};
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}
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test "decodes the common class codes" {
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const std = @import("std");
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const eq = std.testing.expectEqualStrings;
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const isa = ClassCode.unpack(0x06_01_00);
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try std.testing.expectEqual(@as(u8, 0x06), isa.base);
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try std.testing.expectEqual(@as(u8, 0x01), isa.subclass);
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try eq("Bridge", className(isa.base));
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try eq("ISA Bridge", subclassName(isa.base, isa.subclass));
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const ahci = ClassCode.unpack(0x01_06_01);
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try eq("Mass Storage Controller", className(ahci.base));
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try eq("Serial ATA Controller", subclassName(ahci.base, ahci.subclass));
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try eq("AHCI 1.0", progIfName(ahci.base, ahci.subclass, ahci.prog_if));
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const xhci = ClassCode.unpack(0x0C_03_30);
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try eq("USB Controller", subclassName(xhci.base, xhci.subclass));
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try eq("XHCI (USB3) Controller", progIfName(xhci.base, xhci.subclass, xhci.prog_if));
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// Unknowns and the "Other" convention.
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try eq("Other", subclassName(0x02, 0x80));
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try eq("Unknown", subclassName(0x06, 0x7E));
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try eq("", progIfName(0x06, 0x00, 0x00)); // host bridge: prog-IF has no standard name
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}
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