78 lines
3.8 KiB
Zig
78 lines
3.8 KiB
Zig
//! Per-CPU data reached through the GS segment base. The GS base holds a pointer
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//! to this core's `ArchitecturePerCpu`, so kernel code gets the running core's block with
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//! a single MSR read (`scheduler()`) and the system_call entry stub gets its kernel stack
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//! with a `%gs`-relative load (no usable stack yet at that point).
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//!
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//! **swapgs discipline.** In ring 0 the GS base points here; in ring 3 it holds
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//! the user's own GS (which ring 3 may set freely), and this pointer lives in the
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//! KERNEL_GS_BASE MSR instead. Every ring-3 -> ring-0 entry (`swapgs` in the
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//! system_call stub and the conditional swapgs in isr_common) brings it back, and
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//! every ring-0 -> ring-3 exit swaps it away. Because the very first ring
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//! transition is always an exit (the kernel starts in ring 0), the swap pairs
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//! keep the invariant without seeding KERNEL_GS_BASE. `scheduler()` is therefore
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//! valid in any ring-0 context and never sees a user-controlled base.
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const std = @import("std");
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const io = @import("io.zig");
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const parameters = @import("parameters");
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const ia32_gs_base = 0xC000_0101;
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/// Layout is load-bearing: the system_call entry stub in isr.s reaches `kernel_rsp`
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/// at `%gs:0` and `scratch` at `%gs:8`. Keep those two first; the asserts below
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/// pin the offsets.
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pub const ArchitecturePerCpu = extern struct {
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kernel_rsp: u64 = 0, // %gs:0 — kernel stack top for system_call entry (== TSS.rsp0)
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scratch: u64 = 0, // %gs:8 — stashes the user rsp during system_call entry
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scheduler: usize = 0, // the scheduler's PerCpu pointer (what `cpuLocal` returns)
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};
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comptime {
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std.debug.assert(@offsetOf(ArchitecturePerCpu, "kernel_rsp") == 0);
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std.debug.assert(@offsetOf(ArchitecturePerCpu, "scratch") == 8);
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}
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var blocks = [_]ArchitecturePerCpu{.{}} ** parameters.maximum_cpus;
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/// Publish core `index`'s per-CPU block: record the scheduler pointer and point
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/// the GS base at the block. Called once per core during bring-up, after the GDT
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/// is loaded (a GS *selector* reload would clobber the base).
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pub fn setLocal(index: usize, scheduler_ptr: usize) void {
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blocks[index].scheduler = scheduler_ptr;
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io.wrmsr(ia32_gs_base, @intFromPtr(&blocks[index]));
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}
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/// The scheduler pointer for the running core (via the GS base). Valid in any
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/// ring-0 context under the swapgs discipline.
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pub fn scheduler() usize {
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return @as(*const ArchitecturePerCpu, @ptrFromInt(io.rdmsr(ia32_gs_base))).scheduler;
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}
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/// Record core `index`'s kernel stack top, used by the system_call entry stub to
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/// switch off the user stack. The scheduler sets this (and TSS.rsp0) whenever it
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/// switches to a user task.
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pub fn setKernelRsp(index: usize, top: usize) void {
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blocks[index].kernel_rsp = top;
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}
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// Fast-system_call MSRs.
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const ia32_efer = 0xC000_0080;
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const ia32_star = 0xC000_0081;
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const ia32_lstar = 0xC000_0082;
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const ia32_sfmask = 0xC000_0084;
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/// Enable the `system_call`/`sysret` fast path on this core (BSP and each AP). EFER.SCE
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/// turns the instructions on; STAR sets the selectors system_call/sysret load; LSTAR
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/// is the entry stub (isr.s); SFMASK clears RFLAGS bits on entry (notably IF —
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/// the handler runs with interrupts off, like the int-gate path). The GDT is laid
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/// out (kernel code 0x08, then user data 0x18 / code 0x20) precisely so these line
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/// up: system_call loads CS 0x08 / SS 0x10; sysret loads CS = base+16 and SS = base+8
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/// with RPL forced to 3, so base 0x10 gives CS 0x23 (user code|3) and SS 0x1B.
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pub fn initSystemCall() void {
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io.wrmsr(ia32_efer, io.rdmsr(ia32_efer) | 1); // SCE
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io.wrmsr(ia32_star, (@as(u64, 0x08) << 32) | (@as(u64, 0x10) << 48));
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const entry = @extern(*const anyopaque, .{ .name = "syscall_entry" });
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io.wrmsr(ia32_lstar, @intFromPtr(entry));
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io.wrmsr(ia32_sfmask, 0x4_0700); // clear IF, TF, DF, AC on entry
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}
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