271 lines
13 KiB
Zig
271 lines
13 KiB
Zig
//! /system/drivers/pci-bus — the PCI bus driver: enumeration moved out of ring 0
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//! (docs/discovery.md). The device manager matches the `pci_host_bridge`
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//! node and spawns one instance per bridge, the bridge's device id as argv[1] —
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//! the same per-device contract as usb-xhci-bus.
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//!
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//! M19.1 (this increment): claim the bridge, map its ECAM window (resource 0;
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//! the bus range and the MMIO apertures follow it), walk every
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//! bus/device/function config header, and log what the walk finds — ending
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//! with "/system/drivers/pci-bus: N functions found", which the `pci-scan` scenario compares
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//! against the kernel's own enumeration. Registration and reports (M19.2), and
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//! the kernel walk's retirement (M19.3), build on this proven-equivalent scan.
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const std = @import("std");
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const runtime = @import("runtime");
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const protocol = runtime.device_manager_protocol;
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const device = runtime.device;
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const pci_class = @import("pci-class");
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fn writeLine(comptime fmt: []const u8, arguments: anytype) void {
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var line: [128]u8 = undefined;
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_ = runtime.system.write(std.fmt.bufPrint(&line, fmt, arguments) catch return);
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}
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/// Log a discovered function with its (class / subclass / prog-IF) triple decoded
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/// to human names — the boot-log breadcrumb that says *what* the hardware is, so
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/// "class 0x01 (Mass Storage Controller) subclass 0x06 (Serial ATA Controller)
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/// progif 0x01 (AHCI 1.0)" reads straight off the log when writing a new driver.
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/// A dedicated wider buffer than `writeLine`'s, since the decoded names are long.
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fn logFunction(bus: u64, dev: u64, function: u64, class_triple: u32) void {
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const cc = pci_class.ClassCode.unpack(@truncate(class_triple));
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const pif = pci_class.progIfName(cc.base, cc.subclass, cc.prog_if);
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var line: [200]u8 = undefined;
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const text = if (pif.len != 0)
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std.fmt.bufPrint(&line, "/system/drivers/pci-bus: {d}:{d}.{d} class 0x{x:0>2} ({s}) subclass 0x{x:0>2} ({s}) progif 0x{x:0>2} ({s})\n", .{ bus, dev, function, cc.base, pci_class.className(cc.base), cc.subclass, pci_class.subclassName(cc.base, cc.subclass), cc.prog_if, pif }) catch return
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else
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std.fmt.bufPrint(&line, "/system/drivers/pci-bus: {d}:{d}.{d} class 0x{x:0>2} ({s}) subclass 0x{x:0>2} ({s}) progif 0x{x:0>2}\n", .{ bus, dev, function, cc.base, pci_class.className(cc.base), cc.subclass, pci_class.subclassName(cc.base, cc.subclass), cc.prog_if }) catch return;
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_ = runtime.system.write(text);
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}
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var bridge_id: u64 = protocol.no_device;
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var ecam_base: usize = 0;
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var ecam_physical: u64 = 0;
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var start_bus: u64 = 0;
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var bus_count: u64 = 0;
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var manager_handle: runtime.ipc.Handle = 0;
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/// One aligned 32-bit read from a function's configuration space.
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fn configRead(bus: u64, dev: u64, function: u64, offset: u64) u32 {
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const address = ecam_base + (((bus - start_bus) << 20) | (dev << 15) | (function << 12) | offset);
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const register: *volatile u32 = @ptrFromInt(address);
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return register.*;
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}
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fn configWrite(bus: u64, dev: u64, function: u64, offset: u64, value: u32) void {
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const address = ecam_base + (((bus - start_bus) << 20) | (dev << 15) | (function << 12) | offset);
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const register: *volatile u32 = @ptrFromInt(address);
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register.* = value;
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}
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fn configRead16(bus: u64, dev: u64, function: u64, offset: u64) u16 {
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const word = configRead(bus, dev, function, offset & ~@as(u64, 3));
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return @truncate(word >> @intCast((offset & 3) * 8));
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}
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fn configWrite16(bus: u64, dev: u64, function: u64, offset: u64, value: u16) void {
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const aligned = offset & ~@as(u64, 3);
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const shift: u5 = @intCast((offset & 3) * 8);
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const word = configRead(bus, dev, function, aligned);
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const mask = @as(u32, 0xFFFF) << shift;
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configWrite(bus, dev, function, aligned, (word & ~mask) | (@as(u32, value) << shift));
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}
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/// Claim the bridge, map the ECAM, hello the manager, then scan.
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fn initialise(endpoint: runtime.ipc.Handle) bool {
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_ = endpoint;
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if (!device.claim(bridge_id)) {
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writeLine("/system/drivers/pci-bus: unable to claim bridge device {d}\n", .{bridge_id});
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return false;
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}
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const buffer = runtime.allocator().alloc(device.DeviceDescriptor, 64) catch {
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_ = runtime.system.write("/system/drivers/pci-bus: out of memory\n");
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return false;
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};
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const total = device.enumerate(buffer);
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const descriptor = for (buffer[0..@min(total, buffer.len)]) |d| {
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if (d.id == bridge_id) break d;
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} else {
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writeLine("/system/drivers/pci-bus: device {d} not in the device tree\n", .{bridge_id});
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return false;
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};
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// Resource 0 is the ECAM window (1 MiB of config space per bus); the bus
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// range rides beside it. The MMIO apertures (M19.0) come after both.
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if (descriptor.resource_count < 2 or descriptor.resources[0].kind != @intFromEnum(device.ResourceKind.memory)) {
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_ = runtime.system.write("/system/drivers/pci-bus: bridge has no ECAM window\n");
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return false;
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}
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const bus_range = for (descriptor.resources[0..@intCast(descriptor.resource_count)]) |resource| {
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if (resource.kind == @intFromEnum(device.ResourceKind.bus_range)) break resource;
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} else {
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_ = runtime.system.write("/system/drivers/pci-bus: bridge has no bus range\n");
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return false;
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};
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start_bus = bus_range.start;
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bus_count = bus_range.len;
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ecam_physical = descriptor.resources[0].start;
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ecam_base = device.mmioMap(bridge_id, 0) orelse {
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_ = runtime.system.write("/system/drivers/pci-bus: ECAM mmio_map failed\n");
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return false;
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};
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// The handshake, then the scan (reports join in M19.2).
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var manager: ?runtime.ipc.Handle = null;
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var tries: u32 = 0;
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while (manager == null and tries < 100) : (tries += 1) {
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manager = runtime.ipc.lookup(.device_manager);
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if (manager == null) runtime.system.sleep(20);
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}
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const h = manager orelse {
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_ = runtime.system.write("/system/drivers/pci-bus: no device manager to hello\n");
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return false;
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};
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const hello = protocol.Hello{ .role = @intFromEnum(protocol.Role.bus), .device_id = bridge_id };
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var reply: [protocol.message_maximum]u8 = undefined;
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const n = runtime.ipc.call(h, std.mem.asBytes(&hello), &reply) catch {
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_ = runtime.system.write("/system/drivers/pci-bus: hello call failed\n");
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return false;
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};
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if (n < protocol.reply_size or std.mem.bytesToValue(protocol.HelloReply, reply[0..protocol.reply_size]).status != 0) {
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_ = runtime.system.write("/system/drivers/pci-bus: hello refused\n");
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return false;
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}
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manager_handle = h;
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scan();
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return true;
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}
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/// The brute-force walk the kernel does today, from ring 3: every bus in the
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/// range, 32 devices, 8 functions; vendor id FFFFh means nothing decodes there,
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/// and only multifunction devices get their functions 1..7 probed.
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fn scan() void {
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var found: u32 = 0;
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var bus: u64 = start_bus;
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while (bus < start_bus + bus_count) : (bus += 1) {
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var dev: u64 = 0;
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while (dev < 32) : (dev += 1) {
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const first = configRead(bus, dev, 0, 0);
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if (first & 0xFFFF == 0xFFFF) continue;
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const multifunction = (configRead(bus, dev, 0, 0x0C) >> 16) & 0x80 != 0;
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var function: u64 = 0;
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while (function < 8) : (function += 1) {
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if (function != 0 and !multifunction) break;
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const vendor_device = configRead(bus, dev, function, 0);
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if (vendor_device & 0xFFFF == 0xFFFF) continue;
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const class_revision = configRead(bus, dev, function, 0x08);
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found += 1;
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logFunction(bus, dev, function, class_revision >> 8);
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registerAndReport(bus, dev, function, class_revision >> 8);
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}
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}
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}
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writeLine("/system/drivers/pci-bus: {d} functions found\n", .{found});
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}
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/// Register one function under the bridge and report it to the manager. The
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/// descriptor mirrors the kernel's own recording byte for byte — config slice
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/// as resource 0, then the sized BARs — so during coexistence the idempotent
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/// device_register (M19.0) returns the kernel's existing node id rather than
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/// growing a duplicate, and the report carries the id drivers already use.
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fn registerAndReport(bus: u64, dev: u64, function: u64, class_triple: u32) void {
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var descriptor = std.mem.zeroes(device.DeviceDescriptor);
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descriptor.class = @intFromEnum(device.DeviceClass.pci_device);
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descriptor.pci_class = class_triple;
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descriptor.resources[0] = .{
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.kind = @intFromEnum(device.ResourceKind.memory),
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.start = ecam_physical + (((bus - start_bus) << 20) | (dev << 15) | (function << 12)),
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.len = 4096,
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};
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descriptor.resource_count = 1;
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// The standard BAR-sizing probe, exactly as the kernel does it: decode off,
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// write all-ones, read the writable mask back, restore. Header type 0 only.
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const header_type = (configRead(bus, dev, function, 0x0C) >> 16) & 0x7F;
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if (header_type == 0) {
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const command = configRead16(bus, dev, function, 0x04);
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configWrite16(bus, dev, function, 0x04, command & ~@as(u16, 0b11));
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var i: u64 = 0;
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while (i < 6) : (i += 1) {
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if (descriptor.resource_count >= 8) break;
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const off = 0x10 + i * 4;
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const original = configRead(bus, dev, function, off);
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if (original == 0) continue;
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const slot: usize = @intCast(descriptor.resource_count);
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if (original & 1 != 0) {
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configWrite(bus, dev, function, off, 0xFFFF_FFFF);
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const readback = configRead(bus, dev, function, off);
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configWrite(bus, dev, function, off, original);
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const mask = readback & 0xFFFF_FFFC;
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const size: u32 = if (mask == 0) 0 else (~mask +% 1) & 0xFFFF;
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if (size == 0) continue; // unimplemented BAR — nothing to register
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descriptor.resources[slot] = .{ .kind = @intFromEnum(device.ResourceKind.io_port), .start = original & 0xFFFF_FFFC, .len = size };
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descriptor.resource_count += 1;
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} else if ((original >> 1) & 0x3 == 2) {
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const original_high = configRead(bus, dev, function, off + 4);
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configWrite(bus, dev, function, off, 0xFFFF_FFFF);
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configWrite(bus, dev, function, off + 4, 0xFFFF_FFFF);
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const lo = configRead(bus, dev, function, off);
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const hi = configRead(bus, dev, function, off + 4);
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configWrite(bus, dev, function, off, original);
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configWrite(bus, dev, function, off + 4, original_high);
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const readback = (@as(u64, hi) << 32) | (lo & 0xFFFF_FFF0);
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const size: u64 = if (readback == 0) 0 else ~readback +% 1;
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i += 1; // consumed the high half regardless
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if (size == 0) continue;
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descriptor.resources[slot] = .{ .kind = @intFromEnum(device.ResourceKind.memory), .start = (@as(u64, original_high) << 32) | (original & 0xFFFF_FFF0), .len = size };
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descriptor.resource_count += 1;
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} else {
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configWrite(bus, dev, function, off, 0xFFFF_FFFF);
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const readback = configRead(bus, dev, function, off);
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configWrite(bus, dev, function, off, original);
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const mask = readback & 0xFFFF_FFF0;
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const size: u32 = if (mask == 0) 0 else ~mask +% 1;
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if (size == 0) continue;
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descriptor.resources[slot] = .{ .kind = @intFromEnum(device.ResourceKind.memory), .start = original & 0xFFFF_FFF0, .len = size };
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descriptor.resource_count += 1;
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}
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}
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configWrite16(bus, dev, function, 0x04, command);
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}
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const registered = device.register(bridge_id, &descriptor) orelse {
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writeLine("/system/drivers/pci-bus: register refused for {d}:{d}.{d}\n", .{ bus, dev, function });
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return;
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};
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const report = protocol.ChildAdded{
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.parent = bridge_id,
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.bus_address = (bus << 8) | (dev << 3) | function,
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.identity = class_triple,
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.device_id = registered,
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};
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var reply: [protocol.message_maximum]u8 = undefined;
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_ = runtime.ipc.call(manager_handle, std.mem.asBytes(&report), &reply) catch {
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writeLine("/system/drivers/pci-bus: child report for {d}:{d}.{d} failed\n", .{ bus, dev, function });
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};
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}
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fn onMessage(message: []const u8, reply: []u8, sender: u32, capability: ?runtime.ipc.Handle) usize {
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_ = message;
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_ = reply;
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_ = sender;
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_ = capability;
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return 0;
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}
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pub fn main(init: runtime.process.Init) void {
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const argument = init.arguments.get(1) orelse return; // bare (ramdisk sweep): stay silent
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bridge_id = std.fmt.parseInt(u64, argument, 10) catch {
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writeLine("/system/drivers/pci-bus: malformed bridge device id '{s}'\n", .{argument});
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return;
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};
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runtime.service.run(protocol.message_maximum, .{
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.init = initialise,
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.on_message = onMessage,
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});
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}
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pub const panic = runtime.panic;
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comptime {
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_ = &runtime.start._start; // pull the runtime entry shim into the image
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}
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