reorg: move mmio into library/device and spell out its API
mmio is device-driver code, so it joins the other domains under
library/device/mmio/ (module name "mmio" unchanged — a pure relocation, only
the build paths move). And its abbreviated function names are spelled out per
docs/coding-standards.md:
read -> readRegister mb -> memoryBarrier
write -> writeRegister rmb -> readMemoryBarrier
wmb -> writeMemoryBarrier
All call sites updated (virtio-gpu, usb-xhci-library, pci.Function); the two
display-driver placeholders import mmio but use nothing, so they're untouched.
Docs (driver-model graph, README layout, drivers.md, the FHS note) follow the
new path and names.
zig build + test green; virtio-gpu, display-native, display-reattach, usb-hid,
usb-hub, usb-storage, pci-scan pass.
This commit is contained in:
Daniel Samson
@@ -428,9 +428,9 @@ pub fn build(b: *std.Build) void {
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// Typed volatile MMIO register access + memory-ordering barriers, for drivers on
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// top of an mmio_map grant. Depends only on `builtin` (arch-conditional barriers);
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// no target set, so it inherits each driver's. See library/mmio/mmio.zig.
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// no target set, so it inherits each driver's. See library/device/mmio/mmio.zig.
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const mmio_module = b.addModule("mmio", .{
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.root_source_file = b.path("library/mmio/mmio.zig"),
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.root_source_file = b.path("library/device/mmio/mmio.zig"),
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});
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// A device driver's view of its claimed PCI function: config-space header fields, BAR
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@@ -969,7 +969,7 @@ pub fn build(b: *std.Build) void {
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"library/device/acpi/aml/aml.zig", // AML parse + interpret, incl. Notify dispatch (M21)
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"library/device/usb/usb-abi.zig", // wire sizes + bit packings + set-up packet encodings
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"library/device/usb/usb-ids.zig", // class/subclass/protocol code assignments
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"library/mmio/mmio.zig", // barriers assemble + registers round-trip
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"library/device/mmio/mmio.zig", // barriers assemble + registers round-trip
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"system/drivers/ps2-bus/scancode.zig", // set-2 decode + keyboard state machine
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"system/drivers/ps2-bus/mouse-packet.zig", // 3-byte mouse packet assembly
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"system/drivers/usb-hid/hid-report.zig", // HID boot-report keyboard/mouse decode
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+2
-3
@@ -245,10 +245,9 @@ system/ → /system danos's own internals (the self-representation)
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fat.zig, engine.zig, on-disk.zig)
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library/ → /lib libraries, one sub-directory each
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runtime/ the danos-native runtime + file API (fs) — the stable application ABI
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mmio/ volatile register access + memory barriers
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device/ device code by domain — model/ pci/ usb/ acpi/ — each a
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device/ device code by domain — mmio/ model/ pci/ usb/ acpi/ — each a
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shareable data module (device-abi, pci-class, usb-abi/ids,
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acpi-ids) plus a logic module (pci, usb, aml)
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acpi-ids) plus a logic module (mmio, pci, usb, aml)
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protocol/ driver↔service wire contracts (vfs block display scanout input
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power device-manager usb-transfer), one module per directory
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boot/ → /boot the loaders
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@@ -87,7 +87,7 @@ A block driver is now **writable, but not yet memory-safe.** Every storage contr
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worth naming is a bus master: it is programmed by handing it the physical address of a
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descriptor ring and left to read and write memory on its own. That ring is exactly what
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**`dma_alloc`** now provides — physically contiguous, pinned, uncacheable, with its
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physical address disclosed — and **`/lib/mmio`**'s barriers order the descriptor writes
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physical address disclosed — and **`/lib/device/mmio`**'s barriers order the descriptor writes
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against the doorbell, and **`msi_bind`** delivers completions. So an AHCI or NVMe driver
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can be written today (the M14/M15 work in [driver-model.md](driver-model.md); the earlier
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"cannot host a block driver at all" is no longer true).
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+13
-13
@@ -106,9 +106,9 @@ module outlived it, which is rather the point.) The pattern generalises directly
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```
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library/
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runtime/ module "runtime" — syscalls, ipc, lifecycle, memory, threads, log, fs
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mmio/ module "mmio" — volatile register access + barriers [M14]
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device/ device code grouped by domain; each domain splits into a shareable
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data module (enums/wire types, std-only) and a logic module (mmio/IPC)
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mmio/ module "mmio" — typed volatile register access + barriers [M14]
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model/ module "device-abi" — DeviceDescriptor, DeviceClass, ResourceKind
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pci/ "pci-class" (data) + "pci" — config/BAR/capability walk (Function)
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usb/ "usb-abi" + "usb-ids" (data) + "usb" — descriptors, control/interrupt/bulk client
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@@ -160,12 +160,12 @@ class driver, the device manager, or the kernel may share them freely.
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`callCap` and `replyWait(..., send_cap)`, and class drivers consume them now: the
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PS/2 keyboard and mouse drivers attach to ps2-bus this way, and `runtime.usb` /
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`runtime.input` open their per-device and subscription channels with `callCap`.
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- **M14** — DMA memory + the memory-ordering layer. `/lib/mmio` gives drivers typed
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volatile access and `mb`/`rmb`/`wmb` (per-arch); `dma_alloc`/`dma_free` grant
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- **M14** — DMA memory + the memory-ordering layer. `/lib/device/mmio` gives drivers typed
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volatile access and `memoryBarrier`/`readMemoryBarrier`/`writeMemoryBarrier` (per-arch); `dma_alloc`/`dma_free` grant
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physically-contiguous, pinned, uncacheable, reclaim-on-teardown buffers with the
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physical address exposed (`pmm.allocContiguous`, a DMA arena, `mapUserDmaInto`).
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`dma_below_4g` caps the address for legacy engines; `dma_write_combining` is accepted
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but falls back to coherent until PAT is programmed. The bus drivers use `/lib/mmio`,
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but falls back to coherent until PAT is programmed. The bus drivers use `/lib/device/mmio`,
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and `dma_alloc` has real consumers now: the xHCI driver's rings and contexts,
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usb-storage's command/status wrappers, virtio-gpu's virtqueue, and the fat
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service's bounce buffer.
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@@ -252,7 +252,7 @@ const dev_ep = ipc.callCap(h, // ... mint a per-device endpoint,
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## M14 — DMA memory and the memory-ordering contract, for HCDs ✅ done
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*Implemented: `/lib/mmio` (typed volatile access + `mb`/`rmb`/`wmb`, per-arch) and
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*Implemented: `/lib/device/mmio` (typed volatile access + `memoryBarrier`/`readMemoryBarrier`/`writeMemoryBarrier`, per-arch) and
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`dma_alloc`/`dma_free` (contiguous, pinned, uncacheable, reclaim-on-teardown, physical
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address exposed). `dma_write_combining` still falls back to coherent — real WC needs
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PAT, a small follow-up. The rest of this section is the original design note.*
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@@ -294,23 +294,23 @@ doorbell.* = i; // volatile store to UC MMIO
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// nothing stops the compiler reordering these; the device reads a stale descriptor
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```
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So the rules, which belong in `library/mmio.zig` and behind `arch`:
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So the rules, which belong in `library/device/mmio/mmio.zig` and behind `arch`:
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| Situation | Required |
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|---|---|
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| MMIO register read/write | `mmio.read` / `mmio.write` (volatile) |
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| Fill DMA descriptor, then ring doorbell | `wmb()` between them |
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| Woken by IRQ, then read what the device wrote | `rmb()` before the read |
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| MMIO write that must complete before the next read | `mb()` |
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| Fill DMA descriptor, then ring doorbell | `writeMemoryBarrier()` between them |
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| Woken by IRQ, then read what the device wrote | `readMemoryBarrier()` before the read |
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| MMIO write that must complete before the next read | `memoryBarrier()` |
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And the per-arch lowering — the reason this must be an `arch` primitive and not a
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sprinkling of `asm volatile`:
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| | x86_64 | aarch64 |
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|---|---|---|
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| `mb()` | `mfence` | `dsb sy` |
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| `rmb()` | `lfence` | `dsb ld` |
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| `wmb()` | `sfence` | `dsb st` |
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| `memoryBarrier()` | `mfence` | `dsb sy` |
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| `readMemoryBarrier()` | `lfence` | `dsb ld` |
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| `writeMemoryBarrier()` | `sfence` | `dsb st` |
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| DMA cache coherency | coherent; nothing to do | **not guaranteed**; needs non-cacheable buffers or cache maintenance |
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x86 is forgiving here — TSO plus strong-uncacheable MMIO means you usually get away
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@@ -318,7 +318,7 @@ with a compiler barrier alone. ARM is not, and [vision.md](vision.md) makes ARM
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condition. Build the abstraction while there is one caller to fix.
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(Zig note: `@fence` was **removed in 0.16**. Use `@atomicRmw(..., .seq_cst)` for a full
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barrier, or per-arch inline asm — which is what `library/mmio.zig` should hide.)
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barrier, or per-arch inline asm — which is what `library/device/mmio/mmio.zig` should hide.)
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## M15 — interrupts for PCI devices ✅ done (MSI)
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+2
-2
@@ -290,8 +290,8 @@ Several things this list used to warn about are now available (see
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[driver-model.md](driver-model.md)): **port I/O** (`io_read`/`io_write`, claim-gated by
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the device's `io_port` resource — direct ring-3 `in`/`out` is still a #GP, so a PS/2 or
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16550 driver goes through these), **DMA memory** (`dma_alloc`: contiguous, pinned,
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uncacheable, physical address exposed), **memory barriers** (`library/mmio`'s
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`mb`/`rmb`/`wmb`, imported as the `mmio` module), **fault isolation** (a ring-3 fault kills only the faulting
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uncacheable, physical address exposed), **memory barriers** (`library/device/mmio`'s
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`memoryBarrier`/`readMemoryBarrier`/`writeMemoryBarrier`, imported as the `mmio` module), **fault isolation** (a ring-3 fault kills only the faulting
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process — `killCurrentProcess` — and the machine keeps running,
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[resilience](resilience.md)), and **reclaim + restart on death** (every path out of a
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process releases its claims and IRQ/MSI bindings — `releaseAllOwnedBy`,
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@@ -1,4 +1,4 @@
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//! /lib/mmio — typed volatile MMIO register access, plus the memory-ordering
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//! /lib/device/mmio — typed volatile MMIO register access, plus the memory-ordering
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//! barriers a device driver needs. Used by drivers on top of an `mmio_map` grant.
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//!
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//! **`volatile` is not a barrier.** In Zig it means only: don't elide this access, and
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@@ -11,13 +11,13 @@
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//! doorbell.* = i; // volatile store to UC MMIO
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//! // nothing orders these; the device can read a stale descriptor
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//!
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//! Put a `wmb()` between them. The barriers lower per-architecture — which is the whole
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//! reason they are a named primitive and not scattered `asm volatile`:
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//! Put a `writeMemoryBarrier()` between them. The barriers lower per-architecture — which
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//! is the whole reason they are a named primitive and not scattered `asm volatile`:
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//!
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//! x86_64 aarch64
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//! mb() mfence dsb sy
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//! rmb() lfence dsb ld
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//! wmb() sfence dsb st
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//! x86_64 aarch64
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//! memoryBarrier() mfence dsb sy
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//! readMemoryBarrier() lfence dsb ld
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//! writeMemoryBarrier() sfence dsb st
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//!
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//! x86 is forgiving (TSO + strong-uncacheable MMIO), so a compiler barrier usually
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//! suffices; ARM is not, and ARM is the win condition (docs/vision.md) — so the
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@@ -29,52 +29,52 @@ const builtin = @import("builtin");
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/// Read a register of type `T` at absolute virtual address `addr` — a location inside
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/// a device's `mmio_map` grant. `volatile`: never elided, never reordered against
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/// another volatile access.
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pub inline fn read(comptime T: type, addr: usize) T {
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pub inline fn readRegister(comptime T: type, addr: usize) T {
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return @as(*const volatile T, @ptrFromInt(addr)).*;
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}
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/// Write `value` of type `T` to the register at absolute virtual address `addr`.
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pub inline fn write(comptime T: type, addr: usize, value: T) void {
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pub inline fn writeRegister(comptime T: type, addr: usize, value: T) void {
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@as(*volatile T, @ptrFromInt(addr)).* = value;
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}
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/// Full barrier: all loads and stores before it are globally visible before any after
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/// it. Use when an MMIO write must complete before a following read.
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pub inline fn mb() void {
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/// Full memory barrier: all loads and stores before it are globally visible before any
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/// after it. Use when an MMIO write must complete before a following read.
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pub inline fn memoryBarrier() void {
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switch (builtin.target.cpu.arch) {
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.x86_64 => asm volatile ("mfence" ::: .{ .memory = true }),
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.aarch64 => asm volatile ("dsb sy" ::: .{ .memory = true }),
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else => @compileError("mmio.mb: unsupported architecture"),
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else => @compileError("mmio.memoryBarrier: unsupported architecture"),
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}
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}
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/// Read barrier: loads before it complete before loads after it. Use after an IRQ
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/// Read memory barrier: loads before it complete before loads after it. Use after an IRQ
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/// wake, before reading what the device wrote to shared memory.
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pub inline fn rmb() void {
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pub inline fn readMemoryBarrier() void {
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switch (builtin.target.cpu.arch) {
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.x86_64 => asm volatile ("lfence" ::: .{ .memory = true }),
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.aarch64 => asm volatile ("dsb ld" ::: .{ .memory = true }),
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else => @compileError("mmio.rmb: unsupported architecture"),
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else => @compileError("mmio.readMemoryBarrier: unsupported architecture"),
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}
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}
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/// Write barrier: stores before it become visible before stores after it. Use between
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/// filling a DMA descriptor in RAM and ringing the device's doorbell.
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pub inline fn wmb() void {
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/// Write memory barrier: stores before it become visible before stores after it. Use
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/// between filling a DMA descriptor in RAM and ringing the device's doorbell.
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pub inline fn writeMemoryBarrier() void {
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switch (builtin.target.cpu.arch) {
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.x86_64 => asm volatile ("sfence" ::: .{ .memory = true }),
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.aarch64 => asm volatile ("dsb st" ::: .{ .memory = true }),
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else => @compileError("mmio.wmb: unsupported architecture"),
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else => @compileError("mmio.writeMemoryBarrier: unsupported architecture"),
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}
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}
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test "barriers emit and registers round-trip through a RAM cell" {
|
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// The barriers must at least assemble for the host arch; ordering can't be unit
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// tested, but a missing/mistyped mnemonic is caught here.
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wmb();
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rmb();
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mb();
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writeMemoryBarrier();
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readMemoryBarrier();
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memoryBarrier();
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var cell: u64 = 0;
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write(u64, @intFromPtr(&cell), 0xDEAD_BEEF);
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try @import("std").testing.expectEqual(@as(u64, 0xDEAD_BEEF), read(u64, @intFromPtr(&cell)));
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writeRegister(u64, @intFromPtr(&cell), 0xDEAD_BEEF);
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try @import("std").testing.expectEqual(@as(u64, 0xDEAD_BEEF), readRegister(u64, @intFromPtr(&cell)));
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}
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+11
-11
@@ -32,23 +32,23 @@ pub const Function = struct {
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}
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|
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pub fn vendorId(self: *const Function) u16 {
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return mmio.read(u16, self.config + pci_class.config_vendor_id);
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return mmio.readRegister(u16, self.config + pci_class.config_vendor_id);
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}
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pub fn deviceId(self: *const Function) u16 {
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return mmio.read(u16, self.config + pci_class.config_device_id);
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return mmio.readRegister(u16, self.config + pci_class.config_device_id);
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}
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pub fn command(self: *const Function) u16 {
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return mmio.read(u16, self.config + pci_class.config_command);
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return mmio.readRegister(u16, self.config + pci_class.config_command);
|
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}
|
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pub fn status(self: *const Function) u16 {
|
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return mmio.read(u16, self.config + pci_class.config_status);
|
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return mmio.readRegister(u16, self.config + pci_class.config_status);
|
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}
|
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|
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/// Set Memory-Space + Bus-Master enable in the command register. Firmware often leaves
|
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/// a secondary display's decode off; a bus-mastering device must enable both.
|
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pub fn enableMemoryAndBusMaster(self: *const Function) void {
|
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const at = self.config + pci_class.config_command;
|
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mmio.write(u16, at, mmio.read(u16, at) | pci_class.command_memory_and_bus_master);
|
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mmio.writeRegister(u16, at, mmio.readRegister(u16, at) | pci_class.command_memory_and_bus_master);
|
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}
|
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|
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/// Decode BAR `bar` (0..5) and map it: read the BAR register, reject I/O-space BARs,
|
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@@ -60,11 +60,11 @@ pub const Function = struct {
|
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if (bar >= 6) return null;
|
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if (self.bar_virtual[bar] != 0) return self.bar_virtual[bar];
|
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|
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const low = mmio.read(u32, self.config + pci_class.config_bar0 + @as(usize, bar) * 4);
|
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const low = mmio.readRegister(u32, self.config + pci_class.config_bar0 + @as(usize, bar) * 4);
|
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if (low & pci_class.bar_io_space != 0) return null; // an I/O-space BAR
|
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var base: u64 = low & pci_class.bar_memory_base_mask;
|
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if ((low & pci_class.bar_type_mask) == pci_class.bar_type_64bit) { // 64-bit: high half is the next dword
|
||||
const high = mmio.read(u32, self.config + pci_class.config_bar0 + (@as(usize, bar) + 1) * 4);
|
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const high = mmio.readRegister(u32, self.config + pci_class.config_bar0 + (@as(usize, bar) + 1) * 4);
|
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base |= @as(u64, high) << 32;
|
||||
}
|
||||
|
||||
@@ -82,7 +82,7 @@ pub const Function = struct {
|
||||
pub fn capabilities(self: *const Function) CapabilityIterator {
|
||||
const present = self.status() & pci_class.status_capabilities_list != 0;
|
||||
const first = if (present)
|
||||
mmio.read(u8, self.config + pci_class.config_capabilities_pointer) & pci_class.capability_pointer_mask
|
||||
mmio.readRegister(u8, self.config + pci_class.config_capabilities_pointer) & pci_class.capability_pointer_mask
|
||||
else
|
||||
0;
|
||||
return .{ .config = self.config, .cursor = first };
|
||||
@@ -90,7 +90,7 @@ pub const Function = struct {
|
||||
};
|
||||
|
||||
/// One capability header. `offset` is the ABSOLUTE virtual address of the header, so the
|
||||
/// caller reads its body with `mmio.read(T, cap.offset + n)`.
|
||||
/// caller reads its body with `mmio.readRegister(T, cap.offset + n)`.
|
||||
pub const Capability = struct { id: u8, offset: usize };
|
||||
|
||||
pub const CapabilityIterator = struct {
|
||||
@@ -102,8 +102,8 @@ pub const CapabilityIterator = struct {
|
||||
if (self.cursor == 0 or self.guard >= 48) return null;
|
||||
self.guard += 1;
|
||||
const at = self.config + self.cursor;
|
||||
const id = mmio.read(u8, at + 0);
|
||||
self.cursor = mmio.read(u8, at + 1) & pci_class.capability_pointer_mask;
|
||||
const id = mmio.readRegister(u8, at + 0);
|
||||
self.cursor = mmio.readRegister(u8, at + 1) & pci_class.capability_pointer_mask;
|
||||
return .{ .id = id, .offset = at };
|
||||
}
|
||||
};
|
||||
|
||||
@@ -162,7 +162,7 @@ const ProducerRing = struct {
|
||||
// holds it) is written after `parameter`/`status`, with a barrier between.
|
||||
slot.parameter = trb.parameter;
|
||||
slot.status = trb.status;
|
||||
mmio.wmb();
|
||||
mmio.writeMemoryBarrier();
|
||||
slot.control = control;
|
||||
const physical = self.region.physical + index * @sizeOf(Trb);
|
||||
self.enqueue_index += 1;
|
||||
@@ -628,10 +628,10 @@ pub const Controller = struct {
|
||||
// interrupter is enabled, so a hot-plug port-change event is silently
|
||||
// dropped otherwise. Enabling it is harmless to a polling driver.
|
||||
write32(self.interrupter(interrupter_management), 1 << 1); // IE
|
||||
mmio.wmb();
|
||||
mmio.writeMemoryBarrier();
|
||||
|
||||
// Run.
|
||||
mmio.wmb();
|
||||
mmio.writeMemoryBarrier();
|
||||
write32(self.operational(op_usbcmd), read32(self.operational(op_usbcmd)) | usbcmd_run | usbcmd_interrupter_enable);
|
||||
if (!waitClear(self.operational(op_usbsts), usbsts_halted)) return null;
|
||||
|
||||
@@ -699,7 +699,7 @@ pub const Controller = struct {
|
||||
/// address of the enqueued TRB (which the Command Completion Event echoes).
|
||||
fn submitCommand(self: *Controller, trb: Trb) u64 {
|
||||
const physical = self.command_ring.push(trb);
|
||||
mmio.wmb();
|
||||
mmio.writeMemoryBarrier();
|
||||
self.ringDoorbell(0, 0); // doorbell 0, target 0 = command ring
|
||||
return physical;
|
||||
}
|
||||
@@ -711,7 +711,7 @@ pub const Controller = struct {
|
||||
const slot = &ring[self.event_ring.dequeue_index];
|
||||
const control = slot.control;
|
||||
if ((control & cycle_bit != 0) == self.event_ring.cycle) {
|
||||
mmio.rmb();
|
||||
mmio.readMemoryBarrier();
|
||||
const event = Trb{ .parameter = slot.parameter, .status = slot.status, .control = control };
|
||||
self.event_ring.dequeue_index += 1;
|
||||
if (self.event_ring.dequeue_index >= trbs_per_ring) {
|
||||
@@ -1216,7 +1216,7 @@ pub const Controller = struct {
|
||||
.control = trbControl(.status_stage, status_direction | (1 << 5)), // DIR | IOC
|
||||
});
|
||||
|
||||
mmio.wmb();
|
||||
mmio.writeMemoryBarrier();
|
||||
self.ringDoorbell(device.slot_id, 1); // DCI 1 = EP0
|
||||
const code = self.awaitTransfer(device.slot_id, 1, @intCast(data.len)) orelse return false;
|
||||
if (code != @intFromEnum(CompletionCode.success) and code != @intFromEnum(CompletionCode.short_packet)) return false;
|
||||
@@ -1457,7 +1457,7 @@ pub const Controller = struct {
|
||||
.status = length,
|
||||
.control = trbControl(.normal, (1 << 5)), // IOC
|
||||
});
|
||||
mmio.wmb();
|
||||
mmio.writeMemoryBarrier();
|
||||
const number: u8 = endpoint.address & 0x0F;
|
||||
const direction_in = endpoint.address & 0x80 != 0;
|
||||
const dci = doorbellContextIndex(number, direction_in);
|
||||
@@ -1507,7 +1507,7 @@ pub const Controller = struct {
|
||||
.status = subscription.max_length,
|
||||
.control = trbControl(.normal, (1 << 5)), // IOC
|
||||
});
|
||||
mmio.wmb();
|
||||
mmio.writeMemoryBarrier();
|
||||
self.ringDoorbell(subscription.slot_id, subscription.dci);
|
||||
}
|
||||
|
||||
|
||||
@@ -102,17 +102,17 @@ var used_shadow: u16 = 0;
|
||||
// --- common-config register access (little-endian MMIO at `common_base`) ---------------
|
||||
|
||||
fn cfgRead(comptime T: type, comptime field: []const u8) T {
|
||||
return mmio.read(T, common_base + @offsetOf(vp.CommonCfg, field));
|
||||
return mmio.readRegister(T, common_base + @offsetOf(vp.CommonCfg, field));
|
||||
}
|
||||
fn cfgWrite(comptime T: type, comptime field: []const u8, value: T) void {
|
||||
mmio.write(T, common_base + @offsetOf(vp.CommonCfg, field), value);
|
||||
mmio.writeRegister(T, common_base + @offsetOf(vp.CommonCfg, field), value);
|
||||
}
|
||||
/// Write a 64-bit common-config register as two 32-bit halves (low then high) — the widest
|
||||
/// access every virtio-pci host is required to accept for the queue-address registers.
|
||||
fn cfgWrite64(comptime field: []const u8, value: u64) void {
|
||||
const at = common_base + @offsetOf(vp.CommonCfg, field);
|
||||
mmio.write(u32, at, @truncate(value));
|
||||
mmio.write(u32, at + 4, @truncate(value >> 32));
|
||||
mmio.writeRegister(u32, at, @truncate(value));
|
||||
mmio.writeRegister(u32, at + 4, @truncate(value >> 32));
|
||||
}
|
||||
fn orStatus(bit: u8) void {
|
||||
cfgWrite(u8, "device_status", cfgRead(u8, "device_status") | bit);
|
||||
@@ -140,12 +140,12 @@ fn submit(request_len: usize, response_len: usize) bool {
|
||||
|
||||
const avail_ring: [*]u16 = @ptrFromInt(ring.virtual + avail_offset + 4);
|
||||
avail_ring[avail_shadow % queue_size] = 0; // head of the chain is descriptor 0
|
||||
mmio.wmb();
|
||||
mmio.writeMemoryBarrier();
|
||||
avail_shadow +%= 1;
|
||||
mmio.write(u16, ring.virtual + avail_offset + 2, avail_shadow); // avail.idx
|
||||
mmio.wmb();
|
||||
mmio.writeRegister(u16, ring.virtual + avail_offset + 2, avail_shadow); // avail.idx
|
||||
mmio.writeMemoryBarrier();
|
||||
|
||||
mmio.write(u16, notify_addr, 0); // ring the control queue's doorbell
|
||||
mmio.writeRegister(u16, notify_addr, 0); // ring the control queue's doorbell
|
||||
return waitUsed();
|
||||
}
|
||||
|
||||
@@ -155,8 +155,8 @@ fn submit(request_len: usize, response_len: usize) bool {
|
||||
fn waitUsed() bool {
|
||||
var tries: u32 = 0;
|
||||
while (tries < 2000) : (tries += 1) {
|
||||
mmio.rmb();
|
||||
const idx = mmio.read(u16, ring.virtual + used_offset + 2); // used.idx
|
||||
mmio.readMemoryBarrier();
|
||||
const idx = mmio.readRegister(u16, ring.virtual + used_offset + 2); // used.idx
|
||||
if (idx != used_shadow) {
|
||||
used_shadow = idx;
|
||||
return true;
|
||||
@@ -231,16 +231,16 @@ fn initialise(endpoint: ipc.Handle) bool {
|
||||
var caps = function.capabilities();
|
||||
while (caps.next()) |cap| {
|
||||
if (cap.id != vp.pci_cap_vendor) continue;
|
||||
const cfg_type = mmio.read(u8, cap.offset + 3);
|
||||
const cfg_type = mmio.readRegister(u8, cap.offset + 3);
|
||||
if (cfg_type != vp.cfg_common and cfg_type != vp.cfg_notify) continue;
|
||||
const bar = mmio.read(u8, cap.offset + 4);
|
||||
const offset = mmio.read(u32, cap.offset + 8);
|
||||
const bar = mmio.readRegister(u8, cap.offset + 4);
|
||||
const offset = mmio.readRegister(u32, cap.offset + 8);
|
||||
if (function.mapBar(bar)) |bar_base| {
|
||||
if (cfg_type == vp.cfg_common) {
|
||||
common_base = bar_base + offset;
|
||||
} else {
|
||||
notify_base = bar_base + offset;
|
||||
notify_multiplier = mmio.read(u32, cap.offset + 16); // virtio_pci_notify_cap tail
|
||||
notify_multiplier = mmio.readRegister(u32, cap.offset + 16); // virtio_pci_notify_cap tail
|
||||
}
|
||||
}
|
||||
}
|
||||
@@ -290,7 +290,7 @@ fn initialise(endpoint: ipc.Handle) bool {
|
||||
std.log.info("command-buffer allocation failed", .{});
|
||||
return false;
|
||||
};
|
||||
mmio.write(u16, ring.virtual + avail_offset, 1); // VIRTQ_AVAIL_F_NO_INTERRUPT: we poll
|
||||
mmio.writeRegister(u16, ring.virtual + avail_offset, 1); // VIRTQ_AVAIL_F_NO_INTERRUPT: we poll
|
||||
cfgWrite(u16, "queue_size", queue_size);
|
||||
cfgWrite64("queue_desc", ring.physical + desc_offset);
|
||||
cfgWrite64("queue_driver", ring.physical + avail_offset);
|
||||
@@ -372,7 +372,7 @@ fn initialise(endpoint: ipc.Handle) bool {
|
||||
}
|
||||
// The scanout surface is CPU-visible RAM: read the pattern back to prove the mapping,
|
||||
// which together with the flush ack above is the automated stand-in for "it's on screen".
|
||||
mmio.rmb();
|
||||
mmio.readMemoryBarrier();
|
||||
if (pixels[0] != testPixel(0) or pixels[pixel_count / 2] != testPixel(@intCast(pixel_count / 2))) {
|
||||
std.log.info("pixel read-back mismatch", .{});
|
||||
return false;
|
||||
@@ -435,7 +435,7 @@ fn readEdid() void {
|
||||
/// the panel. Reused by the V3 self-test and by every compositor present over `.scanout`. V4
|
||||
/// presents the full surface; the damage-rect fast path is a later refinement.
|
||||
fn presentFull() bool {
|
||||
mmio.wmb(); // the surface writes must be visible before the device transfers them
|
||||
mmio.writeMemoryBarrier(); // the surface writes must be visible before the device transfers them
|
||||
{
|
||||
// Transfer the current-mode rectangle from the guest backing to the host resource. The
|
||||
// device uses the resource's (max) width as the row stride, so the top-left rect at
|
||||
|
||||
Reference in New Issue
Block a user