The flip: PCI enumeration leaves the kernel (M19.3)
enumeratePci, addBars, pciConfigurationPtr, and the PciHeader struct are deleted; the kernel seeds only the host bridge, and the ring-3 pci-bus driver's reports are the sole source of PCI function nodes. The manager matches PCI drivers from reported identity, deduped by registered device id so a bus restart never double-spawns. The flip did its job by exposing a latent SMP race: ring-3 device_register made the broker table concurrent for the first time, and mmio_map read it lock-free — under load a torn resource length mapped hpet's window wrong (its user fault) and underflowed r.len-1 into a kernel integer-overflow panic. Fixed: the broker read in mmio_map (and claim) runs under the big kernel lock, the arithmetic rejects zero-length and wrapping windows cleanly, and pci-bus no longer registers unimplemented size-0 BARs. driver-restart hammered 6x, suite 55/55.
This commit is contained in:
Daniel Samson
parent
d26262bf56
commit
af2c766f42
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@ -167,3 +167,13 @@ free; discovery on x86 is partly about *finding* what ARM just tells you.
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- [ipc.md](ipc.md) — the channels that interrupts-as-messages and the device manager
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will ride on.
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- [vision.md](vision.md) — why drivers belong in isolated user space at all.
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## Update (M19.3, 2026-07-13): PCI enumeration left the kernel
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The kernel now seeds only the `pci_host_bridge` node (ECAM window, MMIO
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apertures derived from the memory map's holes, bus range, and the 16-bit I/O
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window). The per-function walk moved to the ring-3 `pci-bus` driver
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([device-manager.md](device-manager.md)): it claims the bridge, repeats the
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ECAM scan through its mmio grant, and `device_register`s what it finds, which
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the device manager mirrors and matches. The ACPI namespace walk follows in M20;
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the static tables (MADT, HPET, MCFG, FADT + `\\_S5`) stay kernel-side.
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@ -96,11 +96,15 @@ branch is green; keep branches; push everything.
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and asserts the PCI node count never grows — plus harness hardening: a
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failing case now preserves its serial as <case>-failed-serial.log, and
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the heavy scenarios run at 150s; suite 55/55).
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- [ ] **M19.3** — the flip: kernel `enumeratePci` call removed (bridge node
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stays); manager matches PCI drivers from reports. One commit. The
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existing xHCI scenarios (`driver-restart`, `usb-report`, `device-list`)
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are the assertion — xhci must come up spawned off a pci-bus report, and
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the suite must not be able to tell the difference. discovery.md updated.
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- [x] **M19.3** — the flip: kernel `enumeratePci`/`addBars`/`PciHeader` all
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deleted (bridge node stays); manager matches PCI drivers from reported
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identity, deduped by registered id. Surfaced and fixed a real SMP race the
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flip created — ring-3 device_register made the broker table concurrent, so
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mmio_map's lock-free read intermittently tore hpet's resource length
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(user fault) and overflowed `r.len-1` into a kernel panic; now the broker
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read is under the big lock and the arithmetic is guarded, and pci-bus
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skips size-0 BARs. discovery.md updated; suite 55/55 (driver-restart
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hammered 6×).
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- [ ] **merge** `feat/pci-bus` → main, push.
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- [ ] **M20.1** — acpi service, parse only (fills the existing placeholder at
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system/services/acpi/acpi.zig): kernel publishes `acpi-tables`
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@ -360,25 +360,6 @@ const Hpet = extern struct {
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page_protection: u8,
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};
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// --- PCI configuration-space header (first 64 bytes, common fields) ---------
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const PciHeader = extern struct {
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vendor_id: u16 align(1),
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device_id: u16 align(1),
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command: u16 align(1),
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status: u16 align(1),
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revision_id: u8,
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prog_if: u8,
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subclass: u8,
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class_code: u8,
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cache_line_size: u8,
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latency_timer: u8,
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/// bit 7 set => multi-function device.
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header_type: u8,
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bist: u8,
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// 0x10 onward (BARs, etc.) depends on header_type; read separately.
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};
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// --- Entry point ------------------------------------------------------------
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/// Discover hardware from the ACPI tables rooted at `rsdp_physical` and populate
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@ -452,7 +433,7 @@ fn handleTable(device_tree: *DeviceTree, hal: Hal, sdt_physical: u64) !void {
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if (std.mem.eql(u8, &sig, &APIC)) {
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try parseMadt(device_tree, header);
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} else if (std.mem.eql(u8, &sig, &MCFG)) {
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try parseMcfg(device_tree, hal, header);
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try parseMcfg(device_tree, header);
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} else if (std.mem.eql(u8, &sig, &HPET)) {
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try parseHpet(device_tree, hal, header);
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} else if (std.mem.eql(u8, &sig, &FACP)) {
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@ -537,7 +518,7 @@ fn parseMadt(device_tree: *DeviceTree, header: *const SystemDescriptorTableHeade
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}
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/// MCFG -> a pci_host_bridge per ECAM segment, then a PCI enumeration underneath.
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fn parseMcfg(device_tree: *DeviceTree, hal: Hal, header: *const SystemDescriptorTableHeader) !void {
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fn parseMcfg(device_tree: *DeviceTree, header: *const SystemDescriptorTableHeader) !void {
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const total: usize = header.length;
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const base: [*]const u8 = @ptrCast(header);
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@ -557,7 +538,11 @@ fn parseMcfg(device_tree: *DeviceTree, hal: Hal, header: *const SystemDescriptor
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// window functions' I/O BARs must register-contain within (M19.2).
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_ = bridge.addResource(.io_port, 0, 1 << 16);
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try enumeratePci(device_tree, bridge, hal, alloc.*);
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// The function walk itself retired to ring 3 (M19.3): the pci-bus
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// driver claims this bridge, repeats the scan through its ECAM grant,
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// and device_registers what it finds — the kernel seeds only the
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// bridge. The scan's equivalence was proven before the hand-off
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// (pci-scan), and the walk's history is in git if archaeology calls.
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}
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}
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@ -587,7 +572,13 @@ fn addBridgeApertures(bridge: *device_model.Device) void {
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var high_end: u64 = 1 << 32;
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for (boot_memory_regions) |region| {
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const end = region.base + region.pages * 4096;
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if (end > high_end) high_end = end;
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// Above 4 GiB only *usable RAM* blocks the aperture: OVMF describes
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// its own 64-bit PCI window as a reserved region and then programs
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// BARs inside it — honoring reserved there would exclude the very
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// space BARs live in. Below 4 GiB every described region blocks (the
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// kernel image, the tables, the ramdisk all live there). Bring-up
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// trust: only the bridge's claimant can register into the aperture.
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if (region.kind == .usable and end > high_end) high_end = end;
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if (region.base >= (1 << 32) or below_count == below.len) continue;
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below[below_count] = .{ .base = region.base, .end = @min(end, 1 << 32) };
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below_count += 1;
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@ -623,106 +614,6 @@ fn addBridgeApertures(bridge: *device_model.Device) void {
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_ = bridge.addResource(.memory, high_end, (@as(u64, 1) << 46) - high_end);
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}
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/// Brute-force scan the ECAM window's bus range for present PCI functions. No
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/// bridge recursion yet: on the ECAM path the host bridge decodes every bus in
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/// the window, so scanning the declared range finds everything QEMU exposes.
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fn enumeratePci(
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device_tree: *DeviceTree,
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bridge: *device_model.Device,
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hal: Hal,
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alloc: McfgAllocation,
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) !void {
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var bus: u16 = alloc.start_bus;
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while (bus <= alloc.end_bus) : (bus += 1) {
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var device: u8 = 0;
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while (device < 32) : (device += 1) {
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const h0: *align(1) const PciHeader = @ptrCast(pciConfigurationPtr(alloc, hal, @intCast(bus), device, 0));
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if (h0.vendor_id == 0xFFFF) continue; // no function 0 => slot empty
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const funcs: u8 = if (h0.header_type & 0x80 != 0) 8 else 1;
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var function: u8 = 0;
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while (function < funcs) : (function += 1) {
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const configuration = pciConfigurationPtr(alloc, hal, @intCast(bus), device, function);
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const h: *align(1) const PciHeader = @ptrCast(configuration);
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if (h.vendor_id == 0xFFFF) continue;
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var nb: [24]u8 = undefined;
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const nm = std.fmt.bufPrint(&nb, "{s}:{x:0>2}:{x:0>2}.{d}", .{
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bridge.name(), bus, device, function,
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}) catch "pcidev";
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const node = try device_tree.addChild(bridge, .pci_device, nm);
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// Resource 0 is the function's own 4 KiB ECAM configuration space. A
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// claimed PCI driver mmio_maps this to reach its command register,
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// BARs, and — the point — its capability list (MSI/MSI-X, PCIe
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// extended caps), without any new syscall. Physical address per the
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// ECAM formula (same as pciConfigurationPtr).
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const config_physical = alloc.base_address +
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(@as(u64, @as(u8, @intCast(bus)) - alloc.start_bus) << 20) +
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(@as(u64, device) << 15) + (@as(u64, function) << 12);
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_ = node.addResource(.memory, config_physical, abi.page_size);
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node.ids.pci_vendor = h.vendor_id;
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node.ids.pci_device = h.device_id;
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node.ids.pci_class = (@as(u24, h.class_code) << 16) |
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(@as(u24, h.subclass) << 8) | h.prog_if;
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node.ids.pci_bdf = (@as(u16, @intCast(bus)) << 8) | (@as(u16, device) << 3) | function;
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// BARs only exist in header type 0 (normal devices), not bridges.
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if (h.header_type & 0x7F == 0) addBars(node, configuration);
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}
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}
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}
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}
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/// Record and size the memory/IO windows named by a device's Base Address
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/// Registers. Sizing is the standard probe: disable decode, write all-ones, read
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/// back the writable (address) bits, restore. `size = ~mask + 1`.
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fn addBars(node: *device_model.Device, configuration: [*]align(1) u8) void {
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// Stop the device decoding its BARs while we transiently write all-ones.
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const command = rd(u16, configuration, 0x04);
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wr(u16, configuration, 0x04, command & ~@as(u16, 0b11));
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var i: usize = 0;
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while (i < 6) : (i += 1) {
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const off = 0x10 + i * 4;
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const orig = rd(u32, configuration, off);
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if (orig == 0) continue;
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if (orig & 1 != 0) {
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// I/O-space BAR (16-bit address space on x86).
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wr(u32, configuration, off, 0xFFFF_FFFF);
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const readback = rd(u32, configuration, off);
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wr(u32, configuration, off, orig);
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const mask = readback & 0xFFFF_FFFC;
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const size: u32 = if (mask == 0) 0 else (~mask +% 1) & 0xFFFF;
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_ = node.addResource(.io_port, orig & 0xFFFF_FFFC, size);
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} else if ((orig >> 1) & 0x3 == 2) {
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// 64-bit memory BAR: this BAR pair spans two configuration slots.
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const orig_hi = rd(u32, configuration, off + 4);
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wr(u32, configuration, off, 0xFFFF_FFFF);
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wr(u32, configuration, off + 4, 0xFFFF_FFFF);
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const lo = rd(u32, configuration, off);
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const hi = rd(u32, configuration, off + 4);
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wr(u32, configuration, off, orig);
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wr(u32, configuration, off + 4, orig_hi);
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const readback = (@as(u64, hi) << 32) | (lo & 0xFFFF_FFF0);
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const size: u64 = if (readback == 0) 0 else ~readback +% 1;
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const address = (@as(u64, orig_hi) << 32) | (orig & 0xFFFF_FFF0);
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_ = node.addResource(.memory, address, size);
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i += 1; // consumed the high half
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} else {
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// 32-bit memory BAR.
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wr(u32, configuration, off, 0xFFFF_FFFF);
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const readback = rd(u32, configuration, off);
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wr(u32, configuration, off, orig);
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const mask = readback & 0xFFFF_FFF0;
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const size: u32 = if (mask == 0) 0 else ~mask +% 1;
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_ = node.addResource(.memory, orig & 0xFFFF_FFF0, size);
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}
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}
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wr(u16, configuration, 0x04, command); // restore decode
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}
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/// HPET -> a timer node with its register block as an MMIO resource, plus the GSI
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/// its comparators can raise.
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///
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@ -1253,16 +1144,6 @@ fn readCntRegister(base: [*]align(1) const u8, len: usize, xoff: usize, legacy_o
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/// The mapped configuration space of one PCI function (its 4 KiB ECAM page). Mapped
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/// writable so BAR sizing can probe it; reads and writes both go through here.
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fn pciConfigurationPtr(alloc: McfgAllocation, hal: Hal, bus: u8, device: u8, function: u8) [*]align(1) u8 {
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const physical = alloc.base_address +
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(@as(u64, bus - alloc.start_bus) << 20) +
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(@as(u64, device) << 15) +
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(@as(u64, function) << 12);
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// Map the configuration page (writable, for BAR sizing) and use the virtual
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// address the HAL hands back.
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return @ptrFromInt(hal.mapMmio(physical, abi.page_size, true));
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}
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/// Read a little-endian integer at `off` from a (possibly unaligned) byte pointer.
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/// x86 is little-endian and native, so an unaligned load suffices.
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fn rd(comptime T: type, bytes: [*]align(1) const u8, off: usize) T {
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@ -1270,12 +1151,6 @@ fn rd(comptime T: type, bytes: [*]align(1) const u8, off: usize) T {
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return p.*;
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}
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/// Write a little-endian integer at `off` through a (possibly unaligned) pointer.
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fn wr(comptime T: type, bytes: [*]align(1) u8, off: usize, value: T) void {
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const p: *align(1) T = @ptrCast(bytes + off);
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p.* = value;
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}
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// --- tests ------------------------------------------------------------------
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test "eisaIdToStr decodes a packed EISA id" {
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@ -180,6 +180,7 @@ fn registerAndReport(bus: u64, dev: u64, function: u64, class_triple: u32) void
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configWrite(bus, dev, function, off, original);
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const mask = readback & 0xFFFF_FFFC;
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const size: u32 = if (mask == 0) 0 else (~mask +% 1) & 0xFFFF;
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if (size == 0) continue; // unimplemented BAR — nothing to register
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descriptor.resources[slot] = .{ .kind = @intFromEnum(device.ResourceKind.io_port), .start = original & 0xFFFF_FFFC, .len = size };
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descriptor.resource_count += 1;
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} else if ((original >> 1) & 0x3 == 2) {
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@ -192,15 +193,17 @@ fn registerAndReport(bus: u64, dev: u64, function: u64, class_triple: u32) void
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configWrite(bus, dev, function, off + 4, original_high);
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const readback = (@as(u64, hi) << 32) | (lo & 0xFFFF_FFF0);
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const size: u64 = if (readback == 0) 0 else ~readback +% 1;
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i += 1; // consumed the high half regardless
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if (size == 0) continue;
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descriptor.resources[slot] = .{ .kind = @intFromEnum(device.ResourceKind.memory), .start = (@as(u64, original_high) << 32) | (original & 0xFFFF_FFF0), .len = size };
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descriptor.resource_count += 1;
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i += 1; // consumed the high half
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} else {
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configWrite(bus, dev, function, off, 0xFFFF_FFFF);
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const readback = configRead(bus, dev, function, off);
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configWrite(bus, dev, function, off, original);
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const mask = readback & 0xFFFF_FFF0;
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const size: u32 = if (mask == 0) 0 else ~mask +% 1;
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if (size == 0) continue;
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descriptor.resources[slot] = .{ .kind = @intFromEnum(device.ResourceKind.memory), .start = original & 0xFFFF_FFF0, .len = size };
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descriptor.resource_count += 1;
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}
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@ -298,6 +298,8 @@ fn systemDeviceEnumerate(state: *architecture.CpuState) void {
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/// device_claim(id) -> 0/-1: take exclusive ownership of a device for this process.
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fn systemDeviceClaim(state: *architecture.CpuState) void {
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const claim_flags = sync.enter();
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defer sync.leave(claim_flags);
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if (devices_broker.claim(architecture.systemCallArg(state, 0), scheduler.current().id))
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architecture.setSystemCallResult(state, 0)
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else
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@ -312,10 +314,22 @@ fn systemMmioMap(state: *architecture.CpuState) void {
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const resource_index = architecture.systemCallArg(state, 1);
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const t = scheduler.current();
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if (t.aspace == 0) return fail(state);
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const owner = devices_broker.ownerOf(device_id) orelse return fail(state);
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if (owner != t.id) return fail(state); // not claimed by this process
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const r = devices_broker.resourceOf(device_id, resource_index) orelse return fail(state);
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// Read the broker table under the lock: ring-3 device_register (M19) now
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// mutates it concurrently on other cores, so a lock-free read here could
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// see a torn resource (and a torn length used to panic the arithmetic
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// below on integer overflow).
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const r = blk: {
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const flags = sync.enter();
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defer sync.leave(flags);
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const owner = devices_broker.ownerOf(device_id) orelse return fail(state);
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if (owner != t.id) return fail(state); // not claimed by this process
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break :blk devices_broker.resourceOf(device_id, resource_index) orelse return fail(state);
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};
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if (r.kind != @intFromEnum(device_abi.ResourceKind.memory)) return fail(state);
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// A zero-length or wrapping window is not mappable — fail cleanly rather
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// than underflow `r.len - 1`.
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if (r.len == 0) return fail(state);
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if (@addWithOverflow(r.start, r.len)[1] != 0) return fail(state);
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if (t.device_map_next == 0) t.device_map_next = device_arena_base;
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const first = r.start & ~@as(u64, page_size - 1);
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@ -451,6 +465,11 @@ fn systemDeviceRegister(state: *architecture.CpuState) void {
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var descriptor: device_abi.DeviceDescriptor = undefined;
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if (!ipc.copyFromUser(t.aspace, descriptor_ptr, std.mem.asBytes(&descriptor))) return fail(state);
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// Under the big kernel lock: the broker's table is also mutated by the
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// death sweep (releaseAllOwnedBy) and read by enumerate on other cores —
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// ring-3 registration (M19) made those genuinely concurrent.
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const flags = sync.enter();
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defer sync.leave(flags);
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const id = devices_broker.register(parent_id, t.id, &descriptor) catch return fail(state);
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architecture.setSystemCallResult(state, id);
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}
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@ -270,20 +270,28 @@ fn discoveryTest() void {
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// M15: every PCI function now carries its own 4 KiB ECAM configuration space as
|
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// resource 0 — the window a driver mmio_maps to walk its capability list (MSI etc).
|
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// M19.3: the kernel seeds only the bridge; functions arrive by the ring-3
|
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// scan (proven equivalent in pci-scan before the walk retired).
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var buffer: [64]device_abi.DeviceDescriptor = undefined;
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const n = @min(devices_broker.enumerate(&buffer), buffer.len);
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var pci_functions: u32 = 0;
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var pci_config_ok = true;
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var bridges: u32 = 0;
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var bridge_shape_ok = false;
|
||||
for (buffer[0..n]) |d| {
|
||||
if (d.class != @intFromEnum(device_abi.DeviceClass.pci_device)) continue;
|
||||
pci_functions += 1;
|
||||
const has_config = d.resource_count >= 1 and
|
||||
d.resources[0].kind == @intFromEnum(device_abi.ResourceKind.memory) and
|
||||
d.resources[0].len == abi.page_size;
|
||||
if (!has_config) pci_config_ok = false;
|
||||
if (d.class != @intFromEnum(device_abi.DeviceClass.pci_host_bridge)) continue;
|
||||
bridges += 1;
|
||||
var has_bus_range = false;
|
||||
var has_io = false;
|
||||
var memory_windows: u32 = 0;
|
||||
for (d.resources[0..@intCast(d.resource_count)]) |resource| {
|
||||
if (resource.kind == @intFromEnum(device_abi.ResourceKind.bus_range)) has_bus_range = true;
|
||||
if (resource.kind == @intFromEnum(device_abi.ResourceKind.io_port)) has_io = true;
|
||||
if (resource.kind == @intFromEnum(device_abi.ResourceKind.memory)) memory_windows += 1;
|
||||
}
|
||||
// ECAM plus at least one MMIO aperture, the bus range, the I/O window.
|
||||
if (has_bus_range and has_io and memory_windows >= 2) bridge_shape_ok = true;
|
||||
}
|
||||
check("PCI functions were enumerated (MCFG/ECAM)", pci_functions >= 1);
|
||||
check("each PCI function exposes its ECAM config space as resource 0", pci_config_ok);
|
||||
check("a PCI host bridge was seeded (MCFG)", bridges >= 1);
|
||||
check("the bridge carries ECAM, apertures, bus range, and the I/O window", bridge_shape_ok);
|
||||
|
||||
// M19.0: every PCI memory resource (config slice and BARs alike) must be
|
||||
// contained in one of its parent bridge's windows — the aperture derivation
|
||||
|
|
@ -1814,20 +1822,16 @@ fn pciScanTest(boot_information: *const BootInformation) void {
|
|||
return;
|
||||
};
|
||||
|
||||
// What the kernel found: the expected marker is built from its own count.
|
||||
// Post-flip (M19.3) ground truth: the kernel no longer enumerates PCI
|
||||
// functions, so equivalence inverts — the broker's function count after
|
||||
// the scan must equal what the driver itself reported finding.
|
||||
var buffer: [64]device_abi.DeviceDescriptor = undefined;
|
||||
const n = @min(devices_broker.enumerate(&buffer), buffer.len);
|
||||
var kernel_count: u32 = 0;
|
||||
var boot_pci: u32 = 0;
|
||||
for (buffer[0..n]) |d| {
|
||||
if (d.class == @intFromEnum(device_abi.DeviceClass.pci_device)) kernel_count += 1;
|
||||
if (d.class == @intFromEnum(device_abi.DeviceClass.pci_device)) boot_pci += 1;
|
||||
}
|
||||
check("the kernel enumerated PCI functions to compare against", kernel_count >= 1);
|
||||
var marker_buffer: [48]u8 = undefined;
|
||||
const marker = std.fmt.bufPrint(&marker_buffer, "pci-bus: {d} functions found", .{kernel_count}) catch {
|
||||
check("marker formatted", false);
|
||||
result();
|
||||
return;
|
||||
};
|
||||
check("the kernel seeded no PCI functions (the walk retired)", boot_pci == 0);
|
||||
|
||||
process.setInitialRamdisk(image);
|
||||
process.write_count = 0;
|
||||
|
|
@ -1841,16 +1845,35 @@ fn pciScanTest(boot_information: *const BootInformation) void {
|
|||
}
|
||||
check("device-manager spawned (test-pci-restart mode)", manager != 0);
|
||||
|
||||
// First scan: the ring-3 count equals the kernel's.
|
||||
// First scan: wait for the driver's count line and parse the number.
|
||||
const count_prefix = "pci-bus: ";
|
||||
const count_suffix = " functions found";
|
||||
var reported: u32 = 0;
|
||||
scheduler.setPriority(1);
|
||||
var deadline = architecture.millis() + 15000;
|
||||
var seen = false;
|
||||
while (architecture.millis() < deadline and !seen) {
|
||||
if (process.write_len >= marker.len and eql(process.write_buffer[0..marker.len], marker)) seen = true;
|
||||
while (architecture.millis() < deadline and reported == 0) {
|
||||
if (process.write_len > count_prefix.len + count_suffix.len and eql(process.write_buffer[0..count_prefix.len], count_prefix)) {
|
||||
const line = process.write_buffer[0..process.write_len];
|
||||
const digits_end = std.mem.indexOf(u8, line, count_suffix) orelse {
|
||||
scheduler.yield();
|
||||
continue;
|
||||
};
|
||||
reported = std.fmt.parseInt(u32, line[count_prefix.len..digits_end], 10) catch 0;
|
||||
}
|
||||
scheduler.yield();
|
||||
}
|
||||
scheduler.setPriority(4);
|
||||
check("the ring-3 scan found exactly the kernel's function count", seen);
|
||||
check("the ring-3 scan reported a function count", reported >= 1);
|
||||
|
||||
// Every reported function was registered: the broker holds exactly them.
|
||||
var registered: [64]device_abi.DeviceDescriptor = undefined;
|
||||
const r = @min(devices_broker.enumerate(®istered), registered.len);
|
||||
var registered_pci: u32 = 0;
|
||||
for (registered[0..r]) |d| {
|
||||
if (d.class == @intFromEnum(device_abi.DeviceClass.pci_device)) registered_pci += 1;
|
||||
}
|
||||
check("the broker holds exactly the reported functions", registered_pci == reported);
|
||||
const kernel_count = reported; // the no-duplicate check below reuses it
|
||||
|
||||
// The restart drill: the manager kills pci-bus after its reports; the
|
||||
// respawn re-claims, re-scans, and re-registers.
|
||||
|
|
@ -1865,9 +1888,11 @@ fn pciScanTest(boot_information: *const BootInformation) void {
|
|||
scheduler.setPriority(4);
|
||||
check("the manager restarted pci-bus", restarted);
|
||||
|
||||
var marker_buffer: [48]u8 = undefined;
|
||||
const marker = std.fmt.bufPrint(&marker_buffer, "pci-bus: {d} functions found", .{reported}) catch "";
|
||||
scheduler.setPriority(1);
|
||||
deadline = architecture.millis() + 15000;
|
||||
seen = false;
|
||||
var seen = false;
|
||||
while (architecture.millis() < deadline and !seen) {
|
||||
if (process.write_len >= marker.len and eql(process.write_buffer[0..marker.len], marker)) seen = true;
|
||||
scheduler.yield();
|
||||
|
|
|
|||
|
|
@ -50,17 +50,26 @@ fn driverFor(d: device.DeviceDescriptor) ?[]const u8 {
|
|||
/// pci-class.zig decodes.
|
||||
const xhci_pci_class: u64 = 0x0C_03_30;
|
||||
|
||||
/// The bus driver that serves a PCI function, or null. A machine can carry
|
||||
/// several identical controllers — one driver instance per device, the id as
|
||||
/// argv[1]. These drivers speak the protocol: a hello is expected.
|
||||
fn pciDriverFor(d: device.DeviceDescriptor) ?[]const u8 {
|
||||
if (d.class != @intFromEnum(device.DeviceClass.pci_device)) return null;
|
||||
return switch (d.pci_class) {
|
||||
/// The driver that serves a *reported* PCI function (M19.3: matching moved
|
||||
/// from the boot snapshot to the bus reports), or null. A machine can carry
|
||||
/// several identical controllers — one driver instance per reported device,
|
||||
/// its registered id as argv[1].
|
||||
fn pciDriverForIdentity(identity: u64) ?[]const u8 {
|
||||
return switch (identity) {
|
||||
xhci_pci_class => "usb-xhci-bus",
|
||||
else => null,
|
||||
};
|
||||
}
|
||||
|
||||
/// Whether some driver entry already serves registered device `device_id` —
|
||||
/// a re-report after a bus restart must not spawn a second instance.
|
||||
fn driverForDevice(device_id: u64) bool {
|
||||
for (&drivers) |*driver| {
|
||||
if (driver.used and driver.device_id == device_id) return true;
|
||||
}
|
||||
return false;
|
||||
}
|
||||
|
||||
// --- supervision -------------------------------------------------------------
|
||||
|
||||
/// How long a protocol driver has to hello after its spawn.
|
||||
|
|
@ -326,11 +335,8 @@ fn initialise(endpoint: runtime.ipc.Handle) bool {
|
|||
addDriver("pci-bus", descriptor.id, true);
|
||||
continue;
|
||||
}
|
||||
if (pciDriverFor(descriptor)) |driver_name| {
|
||||
matched += 1;
|
||||
addDriver(driver_name, descriptor.id, true);
|
||||
continue;
|
||||
}
|
||||
// PCI functions no longer appear in the boot snapshot (M19.3): the
|
||||
// pci-bus driver reports them, and onChildAdded matches from reports.
|
||||
const driver_name = driverFor(descriptor) orelse continue;
|
||||
matched += 1;
|
||||
// Skip a singleton that is already alive (the initial-ramdisk sweep test
|
||||
|
|
@ -396,6 +402,14 @@ fn onChildAdded(message: []const u8, reply: []u8, sender: u32) usize {
|
|||
if (!addChild(report.parent, report.bus_address, report.identity, report.device_id, sender)) status = -1;
|
||||
writeLine("device-manager: child added (device {d} port {d}, identity {d}) by {s}\n", .{ report.parent, report.bus_address, report.identity, driver.name() });
|
||||
if (status == 0) publishEvent(message[0..protocol.child_added_size]);
|
||||
// Matching from reports (M19.3): a registered child whose identity
|
||||
// names a driver gets one, once — re-reports after a bus restart
|
||||
// dedupe on the registered id, exactly like the registrations do.
|
||||
if (status == 0 and report.device_id != protocol.no_device) {
|
||||
if (pciDriverForIdentity(report.identity)) |child_driver| {
|
||||
if (!driverForDevice(report.device_id)) addDriver(child_driver, report.device_id, true);
|
||||
}
|
||||
}
|
||||
} else {
|
||||
status = -1;
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue