Daniel Samson
b7d97ebb5d
The last claimant. The kernel seeds the acpi-tables node, so it sits in the same boot snapshot the manager already scans to find the PCI host bridge — there was never a bootstrap problem, only a lookup nobody had written. The manager claims it and names it in the spawn; the service stops claiming. Every driver in the system now receives its hardware rather than taking it. Two failures on the way, both mine. addDriver puts the device id in argv[1], and the acpi service read argv[1] as a self-verify device-count floor — so handed device 7 it decided it was in test mode, printed "acpi-parse: ok", and never reported a device. The test argument is now floor:N, which a bare id cannot be mistaken for. And acpi-parse spawns the service directly rather than through the manager, so nothing handed it the node. That test now claims and transfers it exactly as the manager does, which is the right shape: the test plays the manager's role instead of the service reaching for hardware. device_claim now has two callers left: the manager, which is the acquirer and should have it, and the display service's GOP path. That is recorded as question 10 — the framebuffer is not a device, so the answer is likely that it leaves the device table rather than being exempted from its rules. Suite 118/118.
725 lines
31 KiB
Zig
725 lines
31 KiB
Zig
//! /system/services/acpi — the ACPI discovery service: the x86 firmware
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//! interpreter, moved out of ring 0 (docs/discovery.md). Claims the
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//! `acpi-tables` node the kernel publishes (the AML blobs, the broad io_port
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//! grant, a broad irq window, the SCI), and runs the **shared AML module** in
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//! ring 3 — the same parser and interpreter the kernel uses.
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//!
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//! It also owns the **event side** (M21): it registers the domain-named `.power`
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//! service, binds the SCI (System Control Interrupt), and on a power-button
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//! fixed event publishes `power_button` to subscribers — and on init's request
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//! writes S5 to power the machine off. The device discovery (M20) and the event
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//! handling both run in one `service.run` loop.
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const std = @import("std");
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const device = @import("driver");
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const channel = @import("channel");
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const ipc = @import("ipc");
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const process = @import("process");
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const service = @import("service");
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const time = @import("time");
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const memory = @import("memory");
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const logging = @import("logging");
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const aml = @import("aml");
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const acpi_ids = @import("acpi-ids");
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const device_manager_protocol = @import("device-manager-protocol");
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const envelope = @import("envelope");
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const power_protocol = @import("power-protocol");
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/// AML opcode/prefix bytes by name (`zero_opcode`, `byte_prefix`, …) — so the `_HID`
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/// integer decode names the opcodes instead of bare 0x0A/0x0B/… (docs/coding-standards.md).
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const opcodes = aml.opcodes;
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// The claimed acpi-tables node and the resource index of its broad io_port
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// window — the Hal routes every port access through this one claim.
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var node_id: u64 = 0;
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var io_resource_index: u64 = 0;
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// The SCI's irq resource index on the node (the len-1 irq, distinct from the
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// broad [0,256) window), for irqBind / irqAck.
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var sci_resource_index: u64 = 0;
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var has_sci = false;
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// PM1 event/control and GPE register ports, read from the FADT copy the kernel
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// publishes on the node (M21). Port 0 means absent.
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var pm1a_evt: u16 = 0;
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var pm1b_evt: u16 = 0;
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var pm1_evt_len: u8 = 0;
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var pm1a_cnt: u16 = 0;
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var pm1b_cnt: u16 = 0;
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var gpe0_blk: u16 = 0;
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var gpe0_len: u8 = 0;
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var gpe1_blk: u16 = 0;
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var gpe1_len: u8 = 0;
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var smi_cmd: u16 = 0;
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var acpi_enable_value: u8 = 0;
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var s5_slp_typ_a: u8 = 0;
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var s5_slp_typ_b: u8 = 0;
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var s5_valid = false;
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// PM1 event-register bits (ACPI): PWRBTN in the status/enable word is bit 8;
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// the control word's SCI_EN is bit 0; SLP_EN is bit 13.
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const pwrbtn_bit: u16 = 1 << 8;
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const sci_en_bit: u32 = 1 << 0;
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const slp_en: u32 = 1 << 13;
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/// The `.power` subscribers, kept by the service harness (P4c): endpoints handed
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/// over as capabilities, each receiving events as buffered messages, each swept
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/// when its task dies. The table remembers which task subscribed, which is what
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/// the shutdown gate below asks — a shutdown request is honored only from a
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/// subscriber (init subscribes; a stray process does not), the soft gate that
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/// stands in for "only the system supervisor may power off" without hardcoding a
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/// pid the kernel's idle tasks would have taken.
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const Subscriptions = service.Subscribers(power_protocol.Protocol, void);
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// Pass-1 registration record (see main): what pass 2 reports.
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const Registered = struct { hid: [8]u8 = .{0} ** 8, hid_len: usize = 0, device_id: u64 = 0, resource_count: u64 = 0 };
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var registered: [64]Registered = undefined;
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var registered_count: usize = 0;
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// A scratch page returned for SystemMemory OperationRegion maps: the service
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// cannot map arbitrary physical memory from ring 3, so such regions are
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// unsupported and degrade to harmless zeros rather than faulting. The M20.2
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// targets (ps2, the legacy devices) use SystemIO and static templates.
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var mmio_scratch: [4096]u8 align(4096) = .{0} ** 4096;
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fn halMapMmio(physical: u64, len: u64, writable: bool) u64 {
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_ = physical;
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_ = len;
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_ = writable;
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return @intFromPtr(&mmio_scratch);
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}
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fn halPioRead(width: u8, port: u16) u32 {
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return device.ioRead(node_id, io_resource_index, port, width) orelse 0;
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}
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fn halPioWrite(width: u8, port: u16, value: u32) void {
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_ = device.ioWrite(node_id, io_resource_index, port, width, value);
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}
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fn findTablesNode(buffer: []device.DeviceDescriptor) ?device.DeviceDescriptor {
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const total = device.enumerate(buffer);
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for (buffer[0..@min(total, buffer.len)]) |d| {
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if (d.class == @intFromEnum(device.DeviceClass.acpi_tables)) return d;
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}
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return null;
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}
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pub fn main(init: process.Init) void {
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// When the acpi-parse scenario spawns this directly, it passes `floor:N` — a
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// device-count floor to self-verify against. The kernel no longer parses AML, so
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// there is no exact count to match; proving the ring-3 parse found at least N
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// Device objects is the check. Deterministic, no log-scraping.
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//
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// The `floor:` prefix matters. argv[1] is the assigned device id for every driver
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// the manager spawns, so a bare number here would be read as a floor — which is
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// exactly what happened when discovery started being given its node: it saw
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// argv[1] = "7", decided it was in self-verify mode, and never reported a device.
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const floor: ?usize = if (init.arguments.get(1)) |a| blk: {
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if (!std.mem.startsWith(u8, a, "floor:")) break :blk null;
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break :blk std.fmt.parseInt(usize, a["floor:".len..], 10) catch null;
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} else null;
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const buffer = memory.allocator().alloc(device.DeviceDescriptor, 64) catch {
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_ = logging.write("/system/services/acpi: out of memory\n");
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return;
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};
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const node = findTablesNode(buffer) orelse {
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_ = logging.write("/system/services/acpi: no acpi-tables node to claim\n");
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return;
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};
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// The node arrived with the spawn: the manager holds it and names it in the call
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// that creates this process. Discovery was the last thing in the system that
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// acquired hardware by naming it rather than being given it
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// (docs/os-development/device-authority.md).
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node_id = node.id;
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// Map the node's resources: the AML blobs (bytecode), the FADT (intact
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// "FACP" header — decision 3), the io_port grant, and the SCI irq.
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var blocks: [8][]const u8 = undefined;
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var block_count: usize = 0;
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var found_io = false;
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var fadt: ?[]const u8 = null;
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for (node.resources[0..@intCast(node.resource_count)], 0..) |resource, index| {
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if (resource.kind == @intFromEnum(device.ResourceKind.io_port) and !found_io) {
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io_resource_index = index;
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found_io = true;
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continue;
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}
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if (resource.kind == @intFromEnum(device.ResourceKind.irq) and resource.len == 1) {
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sci_resource_index = index;
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has_sci = true;
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continue;
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}
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if (resource.kind != @intFromEnum(device.ResourceKind.memory)) continue;
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const base = device.mmioMap(node_id, index) orelse continue;
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const pointer: [*]const u8 = @ptrFromInt(base);
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const bytes = pointer[0..@intCast(resource.len)];
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if (bytes.len >= 4 and std.mem.eql(u8, bytes[0..4], "FACP")) {
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fadt = bytes;
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continue;
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}
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if (block_count == blocks.len) continue;
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blocks[block_count] = bytes;
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block_count += 1;
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}
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if (block_count == 0) {
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_ = logging.write("/system/services/acpi: no AML blobs on the node\n");
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return;
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}
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const result = aml.parse(memory.allocator(), blocks[0..block_count]) catch {
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_ = logging.write("/system/services/acpi: AML parse failed\n");
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return;
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};
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var namespace = result.namespace;
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const devices = aml.deviceCount(&namespace);
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std.log.info("parsed {d} AML blob(s), {d} namespace devices", .{ block_count, devices });
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if (floor) |minimum| {
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if (devices >= minimum) {
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_ = logging.write("acpi-parse: ok\n");
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} else {
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std.log.info("acpi-parse: too few (ring-3 {d} < floor {d})", .{ devices, minimum });
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}
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// Self-verify mode is standalone (no manager); stop before reporting.
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while (true) time.sleepMillis(1000);
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}
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// Register + report the present _HID devices (M20), then set up the power
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// event side (M21), then serve — all in one harness loop. The interpreter
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// and namespace outlive this frame (static), so the harness callbacks can
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// reach them.
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interpreter_arena = std.heap.ArenaAllocator.init(memory.allocator());
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persistent_namespace = namespace;
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global_interpreter = aml.Interpreter.init(&persistent_namespace, .{
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.mapMmio = halMapMmio,
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.pioRead = halPioRead,
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.pioWrite = halPioWrite,
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}, interpreter_arena.allocator());
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readFadt(fadt);
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s5_valid = readSleepS5(&persistent_namespace);
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// Every name this service needs, resolved before it becomes a provider — see
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// `manager_channel`. Best-effort, as it has always been: a standalone
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// bring-up with no device manager still serves power.
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manager_channel = channel.openEndpoint("device-manager");
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service.run(power_protocol.message_maximum, .{
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.service = "power",
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.init = onInit,
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.on_message = onMessage,
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.on_notification = onNotification,
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.subscribers = Subscriptions.hooks,
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});
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}
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/// The device manager's channel, opened **before** this service binds its own
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/// contract — deliberately, and load-bearing.
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///
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/// init is the registrar, and init is also this service's one subscriber: the
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/// moment `power` is bound, init calls us to subscribe. init has a single thread,
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/// so while it is blocked in that call it cannot answer anyone — including us. If
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/// we opened a name after binding, the two could cross: init blocked calling us,
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/// us blocked asking init to resolve a name, neither ever replying. Resolving
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/// everything we need first makes that impossible, because after the bind this
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/// service only ever talks to the device manager (which never calls init) and
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/// then parks in the harness loop, where init's subscribe lands.
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var manager_channel: ?ipc.Handle = null;
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// Static so the harness callbacks (which run after main's stack frame is gone)
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// can reach the namespace and interpreter.
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var persistent_namespace: aml.Namespace = undefined;
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var global_interpreter: aml.Interpreter = undefined;
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var interpreter_arena: std.heap.ArenaAllocator = undefined;
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/// Startup under the harness: register + report the discovered devices to the
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/// manager (M20), then enable ACPI mode and arm the power button (M21).
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fn onInit(endpoint: ipc.Handle) bool {
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registered_count = 0;
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walkDevices(persistent_namespace.root, &global_interpreter);
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const manager = manager_channel;
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var i: usize = 0;
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while (i < registered_count) : (i += 1) {
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const entry = registered[i];
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const hid = entry.hid[0..entry.hid_len];
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// The devices.csv columns (bus=acpi, hid) then the human-readable name — a
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// would-be /system/configuration/devices.csv row read straight off the boot log.
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const desc = acpi_ids.description(hid);
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if (desc.len != 0)
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std.log.info("device {d} bus=acpi hid={s} — {s} ({d} resources)", .{ entry.device_id, hid, desc, entry.resource_count })
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else
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std.log.info("device {d} bus=acpi hid={s} ({d} resources)", .{ entry.device_id, hid, entry.resource_count });
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if (manager) |h| {
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// The registered device id is the packet's target, so the body only
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// says where on the firmware tree the node sits and what it is.
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var report = device_manager_protocol.ChildAdded{
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.bus = @intFromEnum(device_manager_protocol.BusKind.acpi),
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.parent = node_id,
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.bus_address = entry.device_id,
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.identity = 0,
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};
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@memcpy(report.hid[0..entry.hid_len], entry.hid[0..entry.hid_len]);
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var packet: [device_manager_protocol.message_maximum]u8 = undefined;
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if (device_manager_protocol.Protocol.encodeRequest(.child_added, entry.device_id, report, &.{}, &packet)) |framed| {
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var reply: [device_manager_protocol.message_maximum]u8 = undefined;
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_ = ipc.call(h, framed, &reply) catch {};
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}
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}
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}
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std.log.info("reported {d} device(s) to the manager", .{registered_count});
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armPowerButton(endpoint);
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return true;
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}
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// --- power event side (M21) ---------------------------------------------------
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/// Read the PM1 event/control and GPE register ports plus the SMI enable pair
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/// from the FADT copy on the node. Offsets are from the FADT table start (the
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/// SDT header is the first 36 bytes). Prefers the 32-bit port fields; QEMU's
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/// FADT populates them.
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fn readFadt(fadt: ?[]const u8) void {
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const f = fadt orelse {
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_ = logging.write("acpi: no FADT on the node — power events off\n");
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return;
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};
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smi_cmd = @truncate(rd32(f, 48));
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acpi_enable_value = f[52];
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pm1a_evt = @truncate(rd32(f, 56));
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pm1b_evt = @truncate(rd32(f, 60));
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pm1a_cnt = @truncate(rd32(f, 64));
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pm1b_cnt = @truncate(rd32(f, 68));
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gpe0_blk = @truncate(rd32(f, 80));
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gpe1_blk = @truncate(rd32(f, 84));
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pm1_evt_len = if (f.len > 88) f[88] else 4;
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gpe0_len = if (f.len > 92) f[92] else 0;
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gpe1_len = if (f.len > 93) f[93] else 0;
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}
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fn readSleepS5(ns: *aml.Namespace) bool {
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const st = aml.sleepState(ns, 5) orelse return false;
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s5_slp_typ_a = st.slp_typ_a;
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s5_slp_typ_b = st.slp_typ_b;
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return true;
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}
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/// Enable ACPI mode if the firmware isn't already in it, then bind the SCI and
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/// set PWRBTN_EN so the power button raises an interrupt we can see.
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fn armPowerButton(endpoint: ipc.Handle) void {
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if (pm1a_cnt != 0 and (halPioRead(2, pm1a_cnt) & sci_en_bit) == 0 and smi_cmd != 0) {
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// Switch to ACPI mode: write ACPI_ENABLE to the SMI command port, then
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// spin (bounded) until SCI_EN latches.
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halPioWrite(1, smi_cmd, acpi_enable_value);
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var tries: u32 = 0;
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while (tries < 1000 and (halPioRead(2, pm1a_cnt) & sci_en_bit) == 0) : (tries += 1) {
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time.sleepMillis(1);
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}
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}
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if (!has_sci) {
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_ = logging.write("acpi: no SCI resource — power button unavailable\n");
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return;
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}
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if (!device.irqBind(node_id, sci_resource_index, endpoint)) {
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_ = logging.write("acpi: SCI irq_bind failed\n");
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return;
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}
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// PWRBTN_EN lives in the PM1 enable register at evt_blk + evt_len/2.
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if (pm1a_evt != 0) {
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const en_port = pm1a_evt + pm1_evt_len / 2;
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halPioWrite(2, en_port, @as(u16, @truncate(halPioRead(2, en_port))) | pwrbtn_bit);
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}
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if (pm1b_evt != 0) {
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const en_port = pm1b_evt + pm1_evt_len / 2;
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halPioWrite(2, en_port, @as(u16, @truncate(halPioRead(2, en_port))) | pwrbtn_bit);
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}
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_ = logging.write("acpi: power button armed\n");
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}
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/// The SCI fired. Read PM1 status; a set PWRBTN_STS is the power button — clear
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/// it (write-1), publish, log. Any other set status is cleared and logged
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/// (GPE/Notify dispatch is M21.2). Always re-arm the line.
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fn onSci() void {
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var handled = false;
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inline for (.{ pm1a_evt, pm1b_evt }) |evt_port| {
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if (evt_port != 0) {
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const sts: u16 = @truncate(halPioRead(2, evt_port));
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if (sts & pwrbtn_bit != 0) {
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halPioWrite(2, evt_port, pwrbtn_bit); // write-1-to-clear
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handled = true;
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} else if (sts != 0) {
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halPioWrite(2, evt_port, sts); // clear whatever else latched
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}
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}
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}
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if (handled) {
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_ = logging.write("power: button pressed\n");
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publishButton();
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}
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handleGpe();
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_ = device.irqAck(node_id, sci_resource_index);
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}
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/// General-purpose events: for each set+enabled GPE bit, evaluate its `\_GPE`
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/// handler method (`_Lxx` level / `_Exx` edge), drain the Notify queue the
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/// method produced, and publish an event per notified device. Then clear the
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/// status bit. QEMU raises no GPEs on this config, so this path is exercised by
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/// host unit tests (docs/acpi.md — ACPI events); on real hardware it carries
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/// battery/AC/lid. The embedded controller's `_Qxx` queries are out of scope.
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fn handleGpe() void {
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handleGpeBlock(gpe0_blk, gpe0_len, 0);
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handleGpeBlock(gpe1_blk, gpe1_len, gpe0_len * 4);
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}
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fn handleGpeBlock(blk: u16, len: u8, gpe_base: u32) void {
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if (blk == 0 or len == 0) return;
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const status_bytes = len / 2; // status half, then enable half
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var byte_index: u8 = 0;
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while (byte_index < status_bytes) : (byte_index += 1) {
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const sts: u8 = @truncate(halPioRead(1, blk + byte_index));
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const en: u8 = @truncate(halPioRead(1, blk + status_bytes + byte_index));
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const active = sts & en;
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if (active == 0) continue;
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var bit: u3 = 0;
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while (true) : (bit += 1) {
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if (active & (@as(u8, 1) << bit) != 0) {
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dispatchGpe(gpe_base + @as(u32, byte_index) * 8 + bit);
|
|
}
|
|
if (bit == 7) break;
|
|
}
|
|
halPioWrite(1, blk + byte_index, active); // write-1-to-clear the serviced bits
|
|
}
|
|
}
|
|
|
|
/// Evaluate the `\_GPE._L%02X` or `_E%02X` handler for GPE number `n`, then
|
|
/// publish an event for each device it notified.
|
|
fn dispatchGpe(n: u32) void {
|
|
const gpe_scope = aml.Namespace.resolve(&persistent_namespace, persistent_namespace.root, true, 0, &.{seg4("_GPE")}) orelse return;
|
|
var name: [4]u8 = .{ '_', 'L', 0, 0 };
|
|
writeHex2(name[2..4], n);
|
|
var method = aml.Namespace.childOf(gpe_scope, name);
|
|
if (method == null) {
|
|
name[1] = 'E';
|
|
method = aml.Namespace.childOf(gpe_scope, name);
|
|
}
|
|
const m = method orelse return; // no handler — the status bit was already cleared
|
|
_ = global_interpreter.evaluate(m, &.{}) catch return;
|
|
for (global_interpreter.takeNotifications()) |event| publishNotify(event.node, event.code);
|
|
}
|
|
|
|
fn publishNotify(node: *aml.Node, code: u64) void {
|
|
// Map the notified device's _HID to a domain event where we recognize it.
|
|
// The kind IS the packet's verb, so the mapping picks which event to frame
|
|
// rather than which tag to put in a payload.
|
|
var hid: [8]u8 = .{0} ** 8;
|
|
if (readHid(node, &global_interpreter)) |h| hid = h;
|
|
const notice = power_protocol.Notice{ .code = @truncate(code), .hid = hid };
|
|
std.log.info("power: notify {s} code {d}", .{ hid[0..7], code });
|
|
if (std.mem.eql(u8, hid[0..7], "PNP0C0A")) {
|
|
Subscriptions.publish(.battery, 0, notice);
|
|
} else if (std.mem.eql(u8, hid[0..7], "ACPI0003")) {
|
|
Subscriptions.publish(.ac, 0, notice);
|
|
} else if (std.mem.eql(u8, hid[0..7], "PNP0C0D")) {
|
|
Subscriptions.publish(.lid, 0, notice);
|
|
} else {
|
|
Subscriptions.publish(.notify, 0, notice);
|
|
}
|
|
}
|
|
|
|
/// Two lowercase hex digits of `n` into `out[0..2]`.
|
|
fn writeHex2(out: []u8, n: u32) void {
|
|
const digits = "0123456789ABCDEF";
|
|
out[0] = digits[(n >> 4) & 0xF];
|
|
out[1] = digits[n & 0xF];
|
|
}
|
|
|
|
fn publishButton() void {
|
|
// The kind is the packet's operation, so the harness frames it once and pushes
|
|
// the same bytes to every subscriber. There is no class here: a power event
|
|
// goes to everyone who asked for power events.
|
|
Subscriptions.publish(.power_button, 0, .{});
|
|
}
|
|
|
|
/// Enter S5 (soft off): write SLP_TYP|SLP_EN to the PM1 control register(s).
|
|
/// The kernel has no S5 path — soft-off is owned here, from the service's own
|
|
/// AML parse. Only reached from a PID-1 shutdown request (M21.3).
|
|
fn enterS5() void {
|
|
if (!s5_valid or pm1a_cnt == 0) {
|
|
_ = logging.write("power: S5 unavailable\n");
|
|
return;
|
|
}
|
|
_ = logging.write("power: entering S5\n");
|
|
halPioWrite(2, pm1a_cnt, (@as(u32, s5_slp_typ_a & 0x7) << 10) | slp_en);
|
|
if (pm1b_cnt != 0) halPioWrite(2, pm1b_cnt, (@as(u32, s5_slp_typ_b & 0x7) << 10) | slp_en);
|
|
// If control returns, the write did not take — say so instead of hanging.
|
|
time.sleepMillis(500);
|
|
_ = logging.write("power: S5 write did not take\n");
|
|
}
|
|
|
|
// --- harness callbacks --------------------------------------------------------
|
|
|
|
fn onNotification(badge: u64) void {
|
|
// Two kinds of notification reach this loop now. The SCI is the one this
|
|
// service binds; the published process exits are the harness's, which it has
|
|
// already used to sweep the subscriber table before calling here. Everything
|
|
// that is not a bare IRQ badge must therefore be ignored — treating a death
|
|
// as an interrupt would clear PM1 status the firmware never set.
|
|
if (badge & (ipc.notify_exit_bit | ipc.notify_timer_bit | ipc.notify_message_bit | ipc.notify_signal_bit) != 0) return;
|
|
onSci();
|
|
}
|
|
|
|
const Invocation = envelope.Invocation;
|
|
const Answer = envelope.Answer;
|
|
|
|
/// The power contract: the reserved `subscribe` (the subscriber's endpoint as
|
|
/// the call's capability, answered by the harness) and `shutdown` (subscribers
|
|
/// only). Device discovery uses a different endpoint — the device manager's — so
|
|
/// nothing here handles a tree report.
|
|
fn onMessage(message: []const u8, reply: []u8, sender: u32, arrived: *ipc.Arrival) usize {
|
|
return Subscriptions.dispatch({}, handlers, message, sender, arrived, reply);
|
|
}
|
|
|
|
/// `subscribe` and `unsubscribe` are absent on purpose: the harness answers both.
|
|
const handlers = Subscriptions.Handlers{ .shutdown = onShutdown };
|
|
|
|
/// Honored only from a power subscriber — init, which has already run the stop
|
|
/// sequence over everything else. The power service is mechanism (write S5);
|
|
/// deciding *when* to shut down and stopping the rest of the system first is
|
|
/// init's policy. The badge is the whole gate: it is kernel-stamped, so nothing
|
|
/// in the packet can claim to be init. The subscriber table moved into the
|
|
/// harness; the question it answers has not changed.
|
|
fn onShutdown(_: void, invocation: Invocation(void), _: Answer(void)) isize {
|
|
if (!Subscriptions.has(invocation.sender)) return -envelope.EPERM;
|
|
enterS5();
|
|
return 0;
|
|
}
|
|
|
|
/// Depth-first walk: register + report each present device with a _HID, then
|
|
/// descend. Scopes (\_SB, \_GPE …) are descended without producing a node.
|
|
fn walkDevices(node: *aml.Node, interpreter: *aml.Interpreter) void {
|
|
var child = node.first_child;
|
|
while (child) |c| : (child = c.next_sibling) {
|
|
if (c.kind != .device) {
|
|
walkDevices(c, interpreter);
|
|
continue;
|
|
}
|
|
if (!devicePresent(interpreter, c)) continue; // absent: skip it and its subtree
|
|
|
|
if (readHid(c, interpreter)) |hid| {
|
|
// Skip PCI roots — pci-bus already reports PCI functions; ACPI adds
|
|
// only the non-PCI _HID devices (docs/device-manager.md — matching). The two
|
|
// roots are named through the shared registry, not bare _HID strings.
|
|
const id = acpi_ids.HardwareId.fromHid(hid[0..7]);
|
|
if (id != .pci_bus and id != .pci_express_root_bridge) {
|
|
registerDevice(c, hid, interpreter);
|
|
}
|
|
}
|
|
walkDevices(c, interpreter);
|
|
}
|
|
}
|
|
|
|
fn registerDevice(node: *aml.Node, hid: [8]u8, interpreter: *aml.Interpreter) void {
|
|
if (registered_count >= registered.len) return;
|
|
var descriptor = std.mem.zeroes(device.DeviceDescriptor);
|
|
descriptor.class = @intFromEnum(device.DeviceClass.acpi_device);
|
|
descriptor.pci_class = device.no_pci_class;
|
|
const hid_len: u64 = std.mem.indexOfScalar(u8, &hid, 0) orelse hid.len;
|
|
descriptor.hid_len = hid_len;
|
|
@memcpy(descriptor.hid[0..@intCast(hid_len)], hid[0..@intCast(hid_len)]);
|
|
applyCrs(&descriptor, node, interpreter);
|
|
|
|
const id = device.register(node_id, &descriptor) catch |e| {
|
|
std.log.warn("register refused for {s}: {s}", .{ hid[0..@intCast(hid_len)], @errorName(e) });
|
|
return;
|
|
};
|
|
registered[registered_count] = .{ .hid = hid, .hid_len = @intCast(hid_len), .device_id = id, .resource_count = descriptor.resource_count };
|
|
registered_count += 1;
|
|
}
|
|
|
|
/// _STA bit 0 (present); absent method or a failed evaluation is treated as
|
|
/// present, per the ACPI rules.
|
|
fn devicePresent(interpreter: *aml.Interpreter, node: *aml.Node) bool {
|
|
const sta = aml.Namespace.childOf(node, seg4("_STA")) orelse return true;
|
|
const obj = interpreter.evaluate(sta, &.{}) catch return true;
|
|
const status = obj.asInteger() catch return true;
|
|
return (status & 0x01) != 0;
|
|
}
|
|
|
|
/// The device's EISA-decoded _HID (e.g. "PNP0303"), or null.
|
|
fn readHid(node: *aml.Node, interpreter: *aml.Interpreter) ?[8]u8 {
|
|
const hid = aml.Namespace.childOf(node, seg4("_HID")) orelse return null;
|
|
var buffer: [8]u8 = .{0} ** 8;
|
|
if (hid.kind == .method) {
|
|
const obj = interpreter.evaluate(hid, &.{}) catch return null;
|
|
switch (obj) {
|
|
.integer => |n| {
|
|
_ = eisaIdToStr(@truncate(n), &buffer);
|
|
return buffer;
|
|
},
|
|
else => return null,
|
|
}
|
|
}
|
|
if (hid.kind != .name or hid.value.len == 0) return null;
|
|
const v = hid.value;
|
|
switch (v[0]) {
|
|
// A static _HID names an integer EISA id: Zero/One/Ones or a Byte/Word/DWord/
|
|
// QWord integer prefix. Anything else is not an integer we can EISA-decode.
|
|
opcodes.zero_opcode, opcodes.one_opcode, opcodes.ones_opcode, opcodes.byte_prefix, opcodes.word_prefix, opcodes.dword_prefix, opcodes.qword_prefix => {
|
|
var p: usize = 0;
|
|
const n = readIntObj(v, &p) orelse return null;
|
|
_ = eisaIdToStr(@truncate(n), &buffer);
|
|
return buffer;
|
|
},
|
|
else => return null,
|
|
}
|
|
}
|
|
|
|
// --- _CRS resource-template decode (ported from the kernel's acpi.zig) --------
|
|
|
|
/// A resource template is a byte list of descriptors. Each starts with a tag byte whose
|
|
/// high bit picks the encoding: a *small* descriptor carries its type in bits [6:3] and
|
|
/// its length in bits [2:0]; a *large* descriptor is the whole tag byte, followed by a
|
|
/// 16-bit length. These are the descriptor types danos decodes into resources — named so
|
|
/// the walk below reads by descriptor, not by 0x04/0x85/… (docs/coding-standards.md).
|
|
const large_descriptor_bit: u8 = 0x80; // set in a tag byte => large descriptor
|
|
const small_length_mask: u8 = 0x07; // low 3 bits of a small tag = body length
|
|
const small_type_shift: u3 = 3; // small type sits in bits [6:3]
|
|
|
|
/// Small resource descriptor types (tag bits [6:3]). Non-exhaustive: an unhandled type
|
|
/// is skipped by its length, not misread.
|
|
const SmallResourceType = enum(u8) {
|
|
irq = 0x04,
|
|
io_port = 0x08,
|
|
fixed_io_port = 0x09,
|
|
end_tag = 0x0F,
|
|
_,
|
|
};
|
|
|
|
/// Large resource descriptor types (the whole tag byte). Non-exhaustive for the same reason.
|
|
const LargeResourceType = enum(u8) {
|
|
memory32 = 0x85,
|
|
memory32_fixed = 0x86,
|
|
extended_irq = 0x89,
|
|
_,
|
|
};
|
|
|
|
fn applyCrs(descriptor: *device.DeviceDescriptor, node: *aml.Node, interpreter: *aml.Interpreter) void {
|
|
const crs = aml.Namespace.childOf(node, seg4("_CRS")) orelse return;
|
|
const obj = interpreter.evaluate(crs, &.{}) catch return;
|
|
const bytes = switch (obj) {
|
|
.buffer => |b| b,
|
|
else => return,
|
|
};
|
|
var i: usize = 0;
|
|
while (i < bytes.len) {
|
|
const tag = bytes[i];
|
|
if (tag & large_descriptor_bit == 0) {
|
|
const len: usize = tag & small_length_mask;
|
|
const body = i + 1;
|
|
if (body + len > bytes.len) break;
|
|
switch (@as(SmallResourceType, @enumFromInt((tag >> small_type_shift) & 0x0F))) {
|
|
.irq => if (len >= 2) { // IRQ mask
|
|
const mask = @as(u16, bytes[body]) | (@as(u16, bytes[body + 1]) << 8);
|
|
var b: usize = 0;
|
|
while (b < 16) : (b += 1) {
|
|
if (mask & (@as(u16, 1) << @intCast(b)) != 0) addResource(descriptor, .irq, b, 1);
|
|
}
|
|
},
|
|
.io_port => if (len >= 7) addResource(descriptor, .io_port, rd16(bytes, body + 1), bytes[body + 6]),
|
|
.fixed_io_port => if (len >= 3) addResource(descriptor, .io_port, rd16(bytes, body), bytes[body + 2]),
|
|
.end_tag => break,
|
|
else => {},
|
|
}
|
|
i = body + len;
|
|
} else {
|
|
if (i + 3 > bytes.len) break;
|
|
const len: usize = @intCast(rd16(bytes, i + 1));
|
|
const body = i + 3;
|
|
if (body + len > bytes.len) break;
|
|
switch (@as(LargeResourceType, @enumFromInt(tag))) {
|
|
.memory32 => if (len >= 17) addResource(descriptor, .memory, rd32(bytes, body + 1), rd32(bytes, body + 13)),
|
|
.memory32_fixed => if (len >= 9) addResource(descriptor, .memory, rd32(bytes, body + 1), rd32(bytes, body + 5)),
|
|
.extended_irq => if (len >= 2) {
|
|
const count = bytes[body + 1];
|
|
var k: usize = 0;
|
|
while (k < count and body + 2 + k * 4 + 4 <= body + len) : (k += 1) {
|
|
addResource(descriptor, .irq, rd32(bytes, body + 2 + k * 4), 1);
|
|
}
|
|
},
|
|
else => {},
|
|
}
|
|
i = body + len;
|
|
}
|
|
}
|
|
}
|
|
|
|
fn addResource(descriptor: *device.DeviceDescriptor, kind: device.ResourceKind, start: u64, len: u64) void {
|
|
if (descriptor.resource_count >= descriptor.resources.len) return;
|
|
descriptor.resources[@intCast(descriptor.resource_count)] = .{ .kind = @intFromEnum(kind), .start = start, .len = len };
|
|
descriptor.resource_count += 1;
|
|
}
|
|
|
|
// --- small helpers ported verbatim from the kernel's acpi.zig ----------------
|
|
|
|
fn seg4(comptime s: *const [4:0]u8) [4]u8 {
|
|
return s[0..4].*;
|
|
}
|
|
|
|
fn hexDigit(n: u8) u8 {
|
|
return if (n < 10) '0' + n else 'A' + (n - 10);
|
|
}
|
|
|
|
fn eisaIdToStr(id: u32, buffer: *[8]u8) []const u8 {
|
|
const b0: u16 = @intCast(id & 0xFF);
|
|
const b1: u16 = @intCast((id >> 8) & 0xFF);
|
|
const b2: u8 = @truncate(id >> 16);
|
|
const b3: u8 = @truncate(id >> 24);
|
|
const mfg = (b0 << 8) | b1;
|
|
buffer[0] = '@' + @as(u8, @intCast((mfg >> 10) & 0x1F));
|
|
buffer[1] = '@' + @as(u8, @intCast((mfg >> 5) & 0x1F));
|
|
buffer[2] = '@' + @as(u8, @intCast(mfg & 0x1F));
|
|
buffer[3] = hexDigit((b2 >> 4) & 0xF);
|
|
buffer[4] = hexDigit(b2 & 0xF);
|
|
buffer[5] = hexDigit((b3 >> 4) & 0xF);
|
|
buffer[6] = hexDigit(b3 & 0xF);
|
|
buffer[7] = 0;
|
|
return buffer[0..7];
|
|
}
|
|
|
|
fn readIntObj(bytes: []const u8, p: *usize) ?u64 {
|
|
if (p.* >= bytes.len) return null;
|
|
const op = bytes[p.*];
|
|
p.* += 1;
|
|
switch (op) {
|
|
opcodes.zero_opcode => return 0,
|
|
opcodes.one_opcode => return 1,
|
|
opcodes.ones_opcode => return 1,
|
|
opcodes.byte_prefix => {
|
|
if (p.* >= bytes.len) return null;
|
|
const v = bytes[p.*];
|
|
p.* += 1;
|
|
return v;
|
|
},
|
|
opcodes.word_prefix => {
|
|
if (p.* + 2 > bytes.len) return null;
|
|
const v = rd16(bytes, p.*);
|
|
p.* += 2;
|
|
return v;
|
|
},
|
|
opcodes.dword_prefix => {
|
|
if (p.* + 4 > bytes.len) return null;
|
|
const v = rd32(bytes, p.*);
|
|
p.* += 4;
|
|
return v;
|
|
},
|
|
else => return null,
|
|
}
|
|
}
|
|
|
|
fn rd16(bytes: []const u8, off: usize) u64 {
|
|
return @as(u64, bytes[off]) | (@as(u64, bytes[off + 1]) << 8);
|
|
}
|
|
|
|
fn rd32(bytes: []const u8, off: usize) u64 {
|
|
return rd16(bytes, off) | (rd16(bytes, off + 2) << 16);
|
|
}
|